Lines Matching defs:Src0
541 Operand *Src0 = Instr->getSrc(0);
544 // Src0 and Src1 have to be zero-, or signed-extended to i32. For Src0,
547 Context.insert<InstCast>(CastKind, Src0_32, Src0);
548 Src0 = Src0_32;
574 assert(Src0->getType() == IceType_i32);
575 Call->addArg(Src0);
602 Operand *Src0 = Instr->getSrc(0);
604 const Type SrcTy = Src0->getType();
626 Call->addArg(Src0);
645 Call->addArg(Src0);
673 Context.insert<InstCast>(InstCast::Zext, Src0AsI32, Src0);
674 Src0 = Src0AsI32;
681 Context.insert<InstCast>(InstCast::Zext, Src0AsI32, Src0);
682 Src0 = Src0AsI32;
687 Call->addArg(Src0);
732 Operand *Src0 = IntrinsicCall->getArg(0);
734 Ctx->getRuntimeHelperFunc(isInt32Asserting32Or64(Src0->getType())
740 Call->addArg(Src0);
742 if (Src0->getType() == IceType_i64) {
2358 Variable *Src0 = Func->makeVariable(IceType_i1);
2359 SafeBoolChain Src0Safe = lowerInt1(Src0, Instr->getSrc(0));
2371 Src0 = legalizeToReg(Src0);
2379 _and(T, Src0, Src1RF);
2382 _orr(T, Src0, Src1RF);
2385 _eor(T, Src0, Src1RF);
2416 : Src0(NonConstOperand(S0, S1)), Src1(ConstOperand(S0, S1)),
2417 Swapped(Src0 == S1 && S0 != S1) {
2418 assert(Src0 != nullptr);
2420 assert(Src0 != Src1 || S0 == S1);
2430 return legalizeToReg(Target, Src0);
2434 return legalizeToReg(Target, Swapped ? Src1 : Src0);
2442 return legalizeToReg(Target, Swapped ? Src0 : Src1);
2448 Operand *const Src0;
2515 return legalizeToReg(Target, Swapped ? Src0 : Src1);
2573 // Src0 and Src1 have already been appropriately extended to an i32, so we
2588 Variable *Dest, Operand *Src0,
2590 Int32Operands SrcsLo(loOperand(Src0), loOperand(Src1));
2591 Int32Operands SrcsHi(hiOperand(Src0), hiOperand(Src1));
3089 Operand *Src0 = legalizeUndef(Instr->getSrc(0));
3092 lowerInt64Arithmetic(Instr->getOp(), Instr->getDest(), Src0, Src1);
3130 Variable *Src0R = legalizeToReg(Src0);
3137 Variable *Src0R = legalizeToReg(Src0);
3144 Variable *Src0R = legalizeToReg(Src0);
3151 Variable *Src0R = legalizeToReg(Src0);
3163 Variable *Src0R = legalizeToReg(Src0);
3178 Variable *Src0R = legalizeToReg(Src0);
3192 Variable *Src0R = legalizeToReg(Src0);
3199 Variable *Src0R = legalizeToReg(Src0);
3208 Int32Operands Srcs(Src0, Src1);
3216 Variable *Src0R = legalizeToReg(Src0);
3302 Variable *Src0R = legalizeToReg(Src0);
3529 Operand *Src0 = Instr->getSrc(0);
3530 assert(Dest->getType() == Src0->getType());
3532 Src0 = legalizeUndef(Src0);
3536 Operand *Src0Lo = legalize(loOperand(Src0), Legal_Reg | Legal_Flex);
3542 Operand *Src0Hi = legalize(hiOperand(Src0), Legal_Reg | Legal_Flex);
3554 NewSrc = legalize(Src0, Legal_Reg | Legal_Flex, Dest->getRegNum());
3559 NewSrc = legalize(Src0, Legal_Reg);
3898 Operand *Src0 = legalizeUndef(Instr->getSrc(0));
3921 auto *Src0R = legalizeToReg(Src0);
3931 if (Src0->getType() == IceType_i32) {
3932 Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex);
3934 } else if (Src0->getType() != IceType_i1) {
3935 Variable *Src0R = legalizeToReg(Src0);
3940 lowerInt1ForSelect(T_Lo, Src0, _m1, _0);
3944 if (Src0->getType() != IceType_i1) {
3952 } else if (Src0->getType() != IceType_i1) {
3954 Variable *Src0R = legalizeToReg(Src0);
3962 lowerInt1ForSelect(T, Src0, _m1, _0);
3972 auto *Src0R = legalizeToReg(Src0);
3984 switch (Src0->getType()) {
3986 assert(Src0->getType() != IceType_i64);
3987 _uxt(T_Lo, legalizeToReg(Src0));
3990 _mov(T_Lo, legalize(Src0, Legal_Reg | Legal_Flex));
3993 SafeBoolChain Safe = lowerInt1(T_Lo, Src0);
4007 } else if (Src0->getType() == IceType_i1) {
4010 SafeBoolChain Safe = lowerInt1(T, Src0);
4019 Variable *Src0R = legalizeToReg(Src0);
4029 auto *Src0R = legalizeToReg(Src0);
4033 if (Src0->getType() == IceType_i64)
4034 Src0 = loOperand(Src0);
4035 Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex);
4052 assert(Src0->getType() == (IsTrunc ? IceType_f64 : IceType_f32));
4053 Variable *Src0R = legalizeToReg(Src0);
4062 Variable *Src0R = legalizeToReg(Src0);
4065 assert(typeElementType(Src0->getType()) == IceType_f32);
4073 const bool Src0IsF32 = isFloat32Asserting32Or64(Src0->getType());
4107 Variable *Src0R = legalizeToReg(Src0);
4115 if (Src0->getType() == IceType_i64) {
4126 if (Src0->getType() != IceType_i32) {
4130 Src0R_32, Src0));
4131 Src0 = Src0R_32;
4133 Variable *Src0R = legalizeToReg(Src0);
4147 Operand *Src0 = Instr->getSrc(0);
4148 if (DestTy == Src0->getType()) {
4149 auto *Assign = InstAssign::create(Func, Dest, Src0);
4161 assert(Src0->getType() == IceType_v8i1);
4166 assert(Src0->getType() == IceType_v16i1);
4172 Variable *Src0R = legalizeToReg(Src0);
4182 assert(Src0->getType() == IceType_f64);
4186 Variable *Src0R = legalizeToReg(Src0);
4198 assert(Src0->getType() == IceType_i64);
4203 lowerAssign(InstAssign::create(Func, Src64, Src0));
4209 assert(Src0->getType() == IceType_i8);
4214 assert(Src0->getType() == IceType_i16);
4223 assert(typeWidthInBytes(DestTy) == typeWidthInBytes(Src0->getType()));
4224 assert(isVectorType(DestTy) == isVectorType(Src0->getType()));
4226 _mov(T, Src0);
4240 Variable *Src0 = legalizeToReg(Instr->getSrc(0));
4246 Variable *TSrc0 = makeReg(Src0->getType());
4253 _mov(TSrc0, Src0);
4358 auto *Src0 = legalizeToReg(Instr->getSrc(0));
4385 _Vc##CC0_V(&T0, (INV_V) ? Src1 : Src0, (INV_V) ? Src0 : Src1); \
4386 _Vc##CC1_V(&T1, (INV_V) ? Src0 : Src1, (INV_V) ? Src1 : Src0); \
4445 TargetARM32::lowerInt64IcmpCond(InstIcmp::ICond Condition, Operand *Src0,
4449 Int32Operands SrcsLo(loOperand(Src0), loOperand(Src1));
4450 Int32Operands SrcsHi(hiOperand(Src0), hiOperand(Src1));
4517 Src1RFLo = legalizeToReg(loOperand(Src0));
4518 Src1RFHi = legalizeToReg(hiOperand(Src0));
4520 Src0RLo = legalizeToReg(loOperand(Src0));
4521 Src0RHi = legalizeToReg(hiOperand(Src0));
4570 TargetARM32::lowerInt32IcmpCond(InstIcmp::ICond Condition, Operand *Src0,
4572 Int32Operands Srcs(Src0, Src1);
4607 TargetARM32::lowerInt8AndInt16IcmpCond(InstIcmp::ICond Condition, Operand *Src0,
4609 Int32Operands Srcs(Src0, Src1);
4610 const int32_t ShAmt = 32 - getScalarIntBitWidth(Src0->getType());
4616 _lsl(Src0R, legalizeToReg(Src0), ShAmtImm);
4657 Operand *Src0,
4659 Src0 = legalizeUndef(Src0);
4691 switch (Src0->getType()) {
4697 return lowerInt8AndInt16IcmpCond(Condition, Src0, Src1);
4699 return lowerInt32IcmpCond(Condition, Src0, Src1);
4701 return lowerInt64IcmpCond(Condition, Src0, Src1);
4711 auto *Src0 = legalizeToReg(Instr->getSrc(0));
4713 const Type SrcTy = Src0->getType();
4742 _mov(Src0T, Src0);
4744 Src0 = Src0Shl;
4765 _Vc##C_V(T, (INV_V) ? Src1 : Src0, (INV_V) ? Src0 : Src1, is_signed); \
4801 Variable *Src0 = legalizeToReg(Instr->getSrc(0));
4813 _mov(T, Src0);
4865 Variable *Src0, Operand *Src1) {
4888 return InstArithmetic::create(Func, Oper, Dest, Src0, Src1);
5326 Variable *Src0 = legalizeToReg(Instr->getArg(0));
5329 _vqadd(T, Src0, Src1, Unsigned);
5388 Variable *Src0 = legalizeToReg(Instr->getArg(0));
5391 _vmlap(T, Src0, Src1);
5398 Variable *Src0 = legalizeToReg(Instr->getArg(0));
5401 _vmulh(T, Src0, Src1, Unsigned);
5420 Variable *Src0 = legalizeToReg(Instr->getArg(0));
5423 _vqsub(T, Src0, Src1, Unsigned);
5431 Variable *Src0 = legalizeToReg(Instr->getArg(0));
5434 _vqmovn2(T, Src0, Src1, Unsigned, Saturating);
5479 Operand *Src0 = formMemoryOperand(Load->getSourceAddress(), Ty);
5484 auto *Assign = InstAssign::create(Func, DestLoad, Src0);
5711 Operand *Src0 = ArithInst->getSrc(0);
5713 auto *Var0 = llvm::dyn_cast<Variable>(Src0);
5715 auto *Const0 = llvm::dyn_cast<ConstantInteger32>(Src0);
5721 assert(llvm::isa<ConstantRelocatable>(Src0));
5936 Operand *Src0 = Instr->getRetValue();
5937 Type Ty = Src0->getType();
5939 Src0 = legalizeUndef(Src0);
5940 Variable *R0 = legalizeToReg(loOperand(Src0), RegARM32::Reg_r0);
5941 Variable *R1 = legalizeToReg(hiOperand(Src0), RegARM32::Reg_r1);
5945 Variable *S0 = legalizeToReg(Src0, RegARM32::Reg_s0);
5948 Variable *D0 = legalizeToReg(Src0, RegARM32::Reg_d0);
5950 } else if (isVectorType(Src0->getType())) {
5951 Variable *Q0 = legalizeToReg(Src0, RegARM32::Reg_q0);
5954 Operand *Src0F = legalize(Src0, Legal_Reg | Legal_Flex);
5978 auto *Src0 = Instr->getSrc(0);
5991 Variable *Src0Var = legalizeToReg(Src0);
6005 Variable *Src0R = legalizeToReg(Src0);
6012 Variable *Src0R = legalizeToReg(Src0);
6020 Variable *Src0R = legalizeToReg(Src0);
6033 Variable *Src0R = legalizeToReg(Src0);
6041 Variable *Src0R = legalizeToReg(Src0);
6056 Variable *Src0R = legalizeToReg(Src0);
6063 Variable *Src0R = legalizeToReg(Src0);
6071 Variable *Src0R = legalizeToReg(Src0);
6079 Variable *Src0R = legalizeToReg(Src0);
6086 Variable *Src0R = legalizeToReg(Src0);
6106 InstExtractElement::create(Func, ExtElmt, Src0, Index));
6195 Operand *Src0 = Instr->getComparison();
6197 if (Src0->getType() == IceType_i64) {
6198 Src0 = legalizeUndef(Src0);
6199 Variable *Src0Lo = legalizeToReg(loOperand(Src0));
6200 Variable *Src0Hi = legalizeToReg(hiOperand(Src0));
6214 Variable *Src0Var = legalizeToReg(Src0);
6215 // If Src0 is not an i32, we left shift it -- see the icmp lowering for the
6218 const size_t ShiftAmt = 32 - getScalarIntBitWidth(Src0->getType());