Lines Matching refs:src1
712 const LogicVRegister& src1,
717 int64_t sa = src1.Int(vform, i);
719 uint64_t ua = src1.Uint(vform, i);
756 const LogicVRegister& src1,
761 return cmp(vform, dst, src1, imm_reg, cond);
767 const LogicVRegister& src1,
771 uint64_t ua = src1.Uint(vform, i);
781 const LogicVRegister& src1,
787 uint64_t ua = src1.UintLeftJustified(vform, i);
812 const LogicVRegister& src1,
815 uzp1(vform, temp1, src1, src2);
816 uzp2(vform, temp2, src1, src2);
824 const LogicVRegister& src1,
827 mul(vform, temp, src1, src2);
835 const LogicVRegister& src1,
838 mul(vform, temp, src1, src2);
846 const LogicVRegister& src1,
850 dst.SetUint(vform, i, src1.Uint(vform, i) * src2.Uint(vform, i));
858 const LogicVRegister& src1,
863 return mul(vform, dst, src1, dup_element(indexform, temp, src2, index));
869 const LogicVRegister& src1,
874 return mla(vform, dst, src1, dup_element(indexform, temp, src2, index));
880 const LogicVRegister& src1,
885 return mls(vform, dst, src1, dup_element(indexform, temp, src2, index));
891 const LogicVRegister& src1,
897 return smull(vform, dst, src1, dup_element(indexform, temp, src2, index));
903 const LogicVRegister& src1,
909 return smull2(vform, dst, src1, dup_element(indexform, temp, src2, index));
915 const LogicVRegister& src1,
921 return umull(vform, dst, src1, dup_element(indexform, temp, src2, index));
927 const LogicVRegister& src1,
933 return umull2(vform, dst, src1, dup_element(indexform, temp, src2, index));
939 const LogicVRegister& src1,
945 return smlal(vform, dst, src1, dup_element(indexform, temp, src2, index));
951 const LogicVRegister& src1,
957 return smlal2(vform, dst, src1, dup_element(indexform, temp, src2, index));
963 const LogicVRegister& src1,
969 return umlal(vform, dst, src1, dup_element(indexform, temp, src2, index));
975 const LogicVRegister& src1,
981 return umlal2(vform, dst, src1, dup_element(indexform, temp, src2, index));
987 const LogicVRegister& src1,
993 return smlsl(vform, dst, src1, dup_element(indexform, temp, src2, index));
999 const LogicVRegister& src1,
1005 return smlsl2(vform, dst, src1, dup_element(indexform, temp, src2, index));
1011 const LogicVRegister& src1,
1017 return umlsl(vform, dst, src1, dup_element(indexform, temp, src2, index));
1023 const LogicVRegister& src1,
1029 return umlsl2(vform, dst, src1, dup_element(indexform, temp, src2, index));
1035 const LogicVRegister& src1,
1041 return sqdmull(vform, dst, src1, dup_element(indexform, temp, src2, index));
1047 const LogicVRegister& src1,
1053 return sqdmull2(vform, dst, src1, dup_element(indexform, temp, src2, index));
1059 const LogicVRegister& src1,
1065 return sqdmlal(vform, dst, src1, dup_element(indexform, temp, src2, index));
1071 const LogicVRegister& src1,
1077 return sqdmlal2(vform, dst, src1, dup_element(indexform, temp, src2, index));
1083 const LogicVRegister& src1,
1089 return sqdmlsl(vform, dst, src1, dup_element(indexform, temp, src2, index));
1095 const LogicVRegister& src1,
1101 return sqdmlsl2(vform, dst, src1, dup_element(indexform, temp, src2, index));
1107 const LogicVRegister& src1,
1112 return sqdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index));
1118 const LogicVRegister& src1,
1123 return sqrdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index));
1141 const LogicVRegister& src1,
1147 PolynomialMult(src1.Uint(vform, i), src2.Uint(vform, i)));
1155 const LogicVRegister& src1,
1162 PolynomialMult(src1.Uint(vform_src, i),
1171 const LogicVRegister& src1,
1179 PolynomialMult(src1.Uint(vform_src, lane_count + i),
1188 const LogicVRegister& src1,
1194 uint64_t ua = src1.UintLeftJustified(vform, i);
1219 const LogicVRegister& src1,
1223 dst.SetUint(vform, i, src1.Uint(vform, i) & src2.Uint(vform, i));
1231 const LogicVRegister& src1,
1235 dst.SetUint(vform, i, src1.Uint(vform, i) | src2.Uint(vform, i));
1243 const LogicVRegister& src1,
1247 dst.SetUint(vform, i, src1.Uint(vform, i) | ~src2.Uint(vform, i));
1255 const LogicVRegister& src1,
1259 dst.SetUint(vform, i, src1.Uint(vform, i) ^ src2.Uint(vform, i));
1267 const LogicVRegister& src1,
1271 dst.SetUint(vform, i, src1.Uint(vform, i) & ~src2.Uint(vform, i));
1296 const LogicVRegister& src1,
1302 uint64_t operand3 = src1.Uint(vform, i);
1312 const LogicVRegister& src1,
1318 uint64_t operand3 = src1.Uint(vform, i);
1328 const LogicVRegister& src1,
1334 uint64_t operand3 = src1.Uint(vform, i);
1344 const LogicVRegister& src1,
1349 int64_t src1_val = src1.Int(vform, i);
1365 const LogicVRegister& src1,
1367 return sminmax(vform, dst, src1, src2, true);
1373 const LogicVRegister& src1,
1375 return sminmax(vform, dst, src1, src2, false);
1381 const LogicVRegister& src1,
1386 const LogicVRegister* src = &src1;
1409 const LogicVRegister& src1,
1411 return sminmaxp(vform, dst, src1, src2, true);
1417 const LogicVRegister& src1,
1419 return sminmaxp(vform, dst, src1, src2, false);
1524 const LogicVRegister& src1,
1529 uint64_t src1_val = src1.Uint(vform, i);
1545 const LogicVRegister& src1,
1547 return uminmax(vform, dst, src1, src2, true);
1553 const LogicVRegister& src1,
1555 return uminmax(vform, dst, src1, src2, false);
1561 const LogicVRegister& src1,
1566 const LogicVRegister* src = &src1;
1589 const LogicVRegister& src1,
1591 return uminmaxp(vform, dst, src1, src2, true);
1597 const LogicVRegister& src1,
1599 return uminmaxp(vform, dst, src1, src2, false);
1912 const LogicVRegister& src1,
1917 int64_t lj_src_val = src1.IntLeftJustified(vform, i);
1932 int64_t src_val = src1.Int(vform, i);
1972 const LogicVRegister& src1,
1977 uint64_t lj_src_val = src1.UintLeftJustified(vform, i);
1984 uint64_t src_val = src1.Uint(vform, i);
2219 const LogicVRegister& src1,
2225 int64_t sr = src1.Int(vform, i) - src2.Int(vform, i);
2229 int64_t sr = src1.Uint(vform, i) - src2.Uint(vform, i);
2240 const LogicVRegister& src1,
2244 absdiff(vform, temp, src1, src2, true);
2252 const LogicVRegister& src1,
2256 absdiff(vform, temp, src1, src2, false);
2403 const LogicVRegister& src1,
2409 result[i] = src1.Uint(vform, i + index);
2845 const LogicVRegister& src1,
2848 uxtl(vform, temp1, src1);
2857 const LogicVRegister& src1,
2860 uxtl2(vform, temp1, src1);
2869 const LogicVRegister& src1,
2873 add(vform, dst, src1, temp);
2880 const LogicVRegister& src1,
2884 add(vform, dst, src1, temp);
2891 const LogicVRegister& src1,
2894 sxtl(vform, temp1, src1);
2903 const LogicVRegister& src1,
2906 sxtl2(vform, temp1, src1);
2915 const LogicVRegister& src1,
2919 add(vform, dst, src1, temp);
2926 const LogicVRegister& src1,
2930 add(vform, dst, src1, temp);
2937 const LogicVRegister& src1,
2940 uxtl(vform, temp1, src1);
2949 const LogicVRegister& src1,
2952 uxtl2(vform, temp1, src1);
2961 const LogicVRegister& src1,
2965 sub(vform, dst, src1, temp);
2972 const LogicVRegister& src1,
2976 sub(vform, dst, src1, temp);
2983 const LogicVRegister& src1,
2986 sxtl(vform, temp1, src1);
2995 const LogicVRegister& src1,
2998 sxtl2(vform, temp1, src1);
3007 const LogicVRegister& src1,
3011 sub(vform, dst, src1, temp);
3018 const LogicVRegister& src1,
3022 sub(vform, dst, src1, temp);
3029 const LogicVRegister& src1,
3032 uxtl(vform, temp1, src1);
3041 const LogicVRegister& src1,
3044 uxtl2(vform, temp1, src1);
3053 const LogicVRegister& src1,
3056 sxtl(vform, temp1, src1);
3065 const LogicVRegister& src1,
3068 sxtl2(vform, temp1, src1);
3077 const LogicVRegister& src1,
3080 uxtl(vform, temp1, src1);
3089 const LogicVRegister& src1,
3092 uxtl2(vform, temp1, src1);
3101 const LogicVRegister& src1,
3104 sxtl(vform, temp1, src1);
3113 const LogicVRegister& src1,
3116 sxtl2(vform, temp1, src1);
3125 const LogicVRegister& src1,
3128 uxtl(vform, temp1, src1);
3137 const LogicVRegister& src1,
3140 uxtl2(vform, temp1, src1);
3149 const LogicVRegister& src1,
3152 sxtl(vform, temp1, src1);
3161 const LogicVRegister& src1,
3164 sxtl2(vform, temp1, src1);
3173 const LogicVRegister& src1,
3176 uxtl(vform, temp1, src1);
3185 const LogicVRegister& src1,
3188 uxtl2(vform, temp1, src1);
3197 const LogicVRegister& src1,
3200 sxtl(vform, temp1, src1);
3209 const LogicVRegister& src1,
3212 sxtl2(vform, temp1, src1);
3221 const LogicVRegister& src1,
3224 uxtl(vform, temp1, src1);
3233 const LogicVRegister& src1,
3236 uxtl2(vform, temp1, src1);
3245 const LogicVRegister& src1,
3248 sxtl(vform, temp1, src1);
3257 const LogicVRegister& src1,
3260 sxtl2(vform, temp1, src1);
3269 const LogicVRegister& src1,
3272 LogicVRegister product = sqdmull(vform, temp, src1, src2);
3279 const LogicVRegister& src1,
3282 LogicVRegister product = sqdmull2(vform, temp, src1, src2);
3289 const LogicVRegister& src1,
3292 LogicVRegister product = sqdmull(vform, temp, src1, src2);
3299 const LogicVRegister& src1,
3302 LogicVRegister product = sqdmull2(vform, temp, src1, src2);
3309 const LogicVRegister& src1,
3312 LogicVRegister product = smull(vform, temp, src1, src2);
3319 const LogicVRegister& src1,
3322 LogicVRegister product = smull2(vform, temp, src1, src2);
3329 const LogicVRegister& src1,
3333 // To avoid this, we use (src1 * src2 + 1 << (esize - 2)) >> (esize - 1)
3334 // which is same as (2 * src1 * src2 + 1 << (esize - 1)) >> esize.
3342 product = src1.Int(vform, i) * src2.Int(vform, i);
3359 const LogicVRegister& src1,
3361 return sqrdmulh(vform, dst, src1, src2, false);
3367 const LogicVRegister& src1,
3370 add(VectorFormatDoubleWidth(vform), temp, src1, src2);
3378 const LogicVRegister& src1,
3381 add(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
3389 const LogicVRegister& src1,
3392 add(VectorFormatDoubleWidth(vform), temp, src1, src2);
3400 const LogicVRegister& src1,
3403 add(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
3411 const LogicVRegister& src1,
3414 sub(VectorFormatDoubleWidth(vform), temp, src1, src2);
3422 const LogicVRegister& src1,
3425 sub(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
3433 const LogicVRegister& src1,
3436 sub(VectorFormatDoubleWidth(vform), temp, src1, src2);
3444 const LogicVRegister& src1,
3447 sub(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
3455 const LogicVRegister& src1,
3461 result[2 * i] = src1.Uint(vform, 2 * i);
3475 const LogicVRegister& src1,
3481 result[2 * i] = src1.Uint(vform, (2 * i) + 1);
3495 const LogicVRegister& src1,
3501 result[2 * i] = src1.Uint(vform, i);
3515 const LogicVRegister& src1,
3521 result[2 * i] = src1.Uint(vform, pairs + i);
3535 const LogicVRegister& src1,
3540 result[i] = src1.Uint(vform, i);
3554 const LogicVRegister& src1,
3559 result[i] = src1.Uint(vform, i);
3931 const LogicVRegister& src1, \
3935 T op1 = src1.Float<T>(i); \
3953 const LogicVRegister& src1, \
3956 FN<float>(vform, dst, src1, src2); \
3959 FN<double>(vform, dst, src1, src2); \
3969 const LogicVRegister& src1,
3972 LogicVRegister product = fmul(vform, temp, src1, src2);
3980 const LogicVRegister& src1,
3984 T op1 = -src1.Float<T>(i);
3995 const LogicVRegister& src1,
3998 frecps<float>(vform, dst, src1, src2);
4001 frecps<double>(vform, dst, src1, src2);
4010 const LogicVRegister& src1,
4014 T op1 = -src1.Float<T>(i);
4025 const LogicVRegister& src1,
4028 frsqrts<float>(vform, dst, src1, src2);
4031 frsqrts<double>(vform, dst, src1, src2);
4040 const LogicVRegister& src1,
4046 T op1 = src1.Float<T>(i);
4079 const LogicVRegister& src1,
4083 fcmp<float>(vform, dst, src1, src2, cond);
4086 fcmp<double>(vform, dst, src1, src2, cond);
4111 const LogicVRegister& src1,
4116 LogicVRegister abs_src1 = fabs_<float>(vform, temp1, src1);
4121 LogicVRegister abs_src1 = fabs_<double>(vform, temp1, src1);
4132 const LogicVRegister& src1,
4136 T op1 = src1.Float<T>(i);
4148 const LogicVRegister& src1,
4151 fmla<float>(vform, dst, src1, src2);
4154 fmla<double>(vform, dst, src1, src2);
4163 const LogicVRegister& src1,
4167 T op1 = -src1.Float<T>(i);
4179 const LogicVRegister& src1,
4182 fmls<float>(vform, dst, src1, src2);
4185 fmls<double>(vform, dst, src1, src2);
4249 const LogicVRegister& src1,
4252 fsub(vform, temp, src1, src2);
4281 const LogicVRegister& src1, \
4284 uzp1(vform, temp1, src1, src2); \
4285 uzp2(vform, temp2, src1, src2); \
4353 const LogicVRegister& src1,
4360 fmul<float>(vform, dst, src1, index_reg);
4365 fmul<double>(vform, dst, src1, index_reg);
4373 const LogicVRegister& src1,
4380 fmla<float>(vform, dst, src1, index_reg);
4385 fmla<double>(vform, dst, src1, index_reg);
4393 const LogicVRegister& src1,
4400 fmls<float>(vform, dst, src1, index_reg);
4405 fmls<double>(vform, dst, src1, index_reg);
4413 const LogicVRegister& src1,
4420 fmulx<float>(vform, dst, src1, index_reg);
4425 fmulx<double>(vform, dst, src1, index_reg);