Searched defs:DestVT (Results 1 - 17 of 17) sorted by relevance

/external/llvm/utils/TableGen/
H A DCallingConvEmitter.cpp223 MVT::SimpleValueType DestVT = getValueType(DestTy); local
224 O << IndentStr << "LocVT = " << getEnumName(DestVT) <<";\n";
225 if (MVT(DestVT).isFloatingPoint()) {
237 MVT::SimpleValueType DestVT = getValueType(DestTy); local
238 O << IndentStr << "LocVT = " << getEnumName(DestVT) << ";\n";
239 if (MVT(DestVT).isFloatingPoint()) {
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypes.cpp924 EVT DestVT) {
928 SDValue StackPtr = DAG.CreateStackTemporary(Op.getValueType(), DestVT);
933 return DAG.getLoad(DestVT, dl, Store, StackPtr, MachinePointerInfo(),
923 CreateStackStoreLoad(SDValue Op, EVT DestVT) argument
H A DLegalizeVectorTypes.cpp246 EVT DestVT = N->getValueType(0).getVectorElementType(); local
265 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
1272 EVT DestVT = N->getValueType(0); local
1274 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1291 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DLegalizeTypes.cpp882 EVT DestVT) {
886 SDValue StackPtr = DAG.CreateStackTemporary(Op.getValueType(), DestVT);
891 return DAG.getLoad(DestVT, dl, Store, StackPtr, MachinePointerInfo(),
881 CreateStackStoreLoad(SDValue Op, EVT DestVT) argument
H A DLegalizeVectorTypes.cpp207 EVT DestVT = N->getValueType(0).getVectorElementType(); local
209 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
H A DTargetLowering.cpp691 EVT DestVT = TLI->getRegisterType(NewVT); local
692 RegisterVT = DestVT;
693 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
694 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
982 EVT DestVT = getRegisterType(Context, NewVT); local
983 RegisterVT = DestVT;
990 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
991 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
H A DSelectionDAGBuilder.cpp2616 EVT DestVT = TLI.getValueType(I.getType()); local
2617 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2629 EVT DestVT = TLI.getValueType(I.getType()); local
2630 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2663 EVT DestVT = TLI.getValueType(I.getType()); local
2664 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2671 EVT DestVT = TLI.getValueType(I.getType()); local
2672 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2679 EVT DestVT = TLI.getValueType(I.getType()); local
2680 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT,
2686 EVT DestVT = TLI.getValueType(I.getType()); local
2694 EVT DestVT = TLI.getValueType(I.getType()); local
2701 EVT DestVT = TLI.getValueType(I.getType()); local
2708 EVT DestVT = TLI.getValueType(I.getType()); local
2715 EVT DestVT = TLI.getValueType(I.getType()); local
2722 EVT DestVT = TLI.getValueType(I.getType()); local
2730 EVT DestVT = TLI.getValueType(I.getType()); local
2738 EVT DestVT = TLI.getValueType(I.getType()); local
2744 EVT DestVT = TLI.getValueType(I.getType()); local
4836 EVT DestVT = TLI.getValueType(I.getType()); local
4865 EVT DestVT = TLI.getValueType(I.getType()); local
[all...]
/external/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1152 MVT DestVT = TLI->getRegisterType(NewVT); local
1153 RegisterVT = DestVT;
1154 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1155 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1549 MVT DestVT = getRegisterType(Context, NewVT); local
1550 RegisterVT = DestVT;
1557 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1558 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
/external/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp139 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
140 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
143 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
145 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
146 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
148 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
953 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local
955 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
1027 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local
1029 if (SrcVT != MVT::f64 || DestVT !
1153 MVT DestVT = VA.getLocVT(); local
1161 MVT DestVT = VA.getLocVT(); local
1530 EVT SrcVT, DestVT; local
1567 MVT DestVT = DestEVT.getSimpleVT(); local
1575 emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1594 emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1609 emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1618 emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1640 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, bool IsZExt) argument
1654 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp164 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
911 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local
913 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
929 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local
931 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1173 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local
1177 if (DestVT != MVT::i16 && DestVT != MVT::i8)
1345 MVT DestVT = VA.getLocVT(); local
1347 (DestVT
1357 MVT DestVT = VA.getLocVT(); local
1412 MVT DestVT = VA.getValVT(); local
1661 MVT DestVT = VA.getLocVT(); local
1714 PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, bool IsZExt) argument
1786 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local
1830 MVT DestVT = DestEVT.getSimpleVT(); local
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMFastISel.cpp1687 EVT DestVT = RVLocs[0].getValVT(); local
1688 TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1998 EVT SrcVT, DestVT; local
2000 DestVT = TLI.getValueType(DestTy, true);
2005 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2016 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT !
[all...]
/external/llvm/lib/Target/ARM/
H A DARMFastISel.cpp175 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1737 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local
1741 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1948 MVT DestVT = VA.getLocVT(); local
1949 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1951 ArgVT = DestVT;
1957 MVT DestVT = VA.getLocVT(); local
1958 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZEx
2035 MVT DestVT = RVLocs[0].getValVT(); local
2122 MVT DestVT = VA.getValVT(); local
2566 EVT SrcVT, DestVT; local
2584 ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument
2739 MVT DestVT = DestEVT.getSimpleVT(); local
[all...]
H A DARMISelLowering.cpp5944 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); local
5952 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
5968 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5974 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5979 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5982 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5985 Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1,
/external/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp188 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
189 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
2742 MVT DestVT; local
2743 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2757 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
2759 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
2762 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
2764 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
2767 DestVT
2775 MVT DestVT; local
2961 MVT DestVT = VA.getLocVT(); local
2971 MVT DestVT = VA.getLocVT(); local
3782 MVT DestVT = DestEVT.getSimpleVT(); local
3835 emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) argument
4244 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool IsZExt) argument
[all...]
H A DAArch64ISelLowering.cpp5013 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); local
5020 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
5035 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5041 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5046 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5049 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5053 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
/external/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp624 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
631 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
2016 EVT DestVT = Op.getValueType(); local
2017 if (DestVT == MVT::f64)
2020 if (DestVT == MVT::f32)
2031 EVT DestVT = Op.getValueType(); local
2032 if (DestVT == MVT::f32)
2035 if (DestVT == MVT::f64)
2570 EVT DestVT = N->getValueType(0); local
2571 if (DestVT
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86ISelLowering.cpp7804 EVT DestVT = Op.getValueType(); local
7806 if (DestVT.bitsLT(MVT::f64)) {
7807 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7809 } else if (DestVT.bitsGT(MVT::f64)) {
7810 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);

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