/external/llvm/lib/Bitcode/Writer/ |
H A D | ValueEnumerator.cpp | 63 for (const Value *Op : C->operands()) 64 if (!isa<BasicBlock>(Op) && !isa<GlobalValue>(Op)) 65 orderValue(Op, OM); 129 for (const Value *Op : I.operands()) 130 if ((isa<Constant>(*Op) && !isa<GlobalValue>(*Op)) || 131 isa<InlineAsm>(*Op)) 132 orderValue(Op, OM); 225 for (const Value *Op 601 auto *Op = cast<MDNode>(*I); local [all...] |
/external/llvm/lib/CodeGen/ |
H A D | Analysis.cpp | 246 Value *Op = I->getOperand(0); local 249 if (isNoopBitcast(Op->getType(), I->getType(), TLI)) 250 NoopInput = Op; 254 NoopInput = Op; 261 cast<IntegerType>(Op->getType())->getBitWidth()) 262 NoopInput = Op; 270 NoopInput = Op; 272 TLI.allowTruncateForTailCall(Op->getType(), I->getType())) { 274 NoopInput = Op; 310 NoopInput = Op; [all...] |
H A D | MIRPrinter.cpp | 121 void printTargetFlags(const MachineOperand &Op); 122 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI, 125 void print(const MachineMemOperand &Op); 593 for (const auto *Op : MI.memoperands()) { 596 print(*Op); 690 void MIPrinter::printTargetFlags(const MachineOperand &Op) { argument 691 if (!Op.getTargetFlags()) 694 Op.getParent()->getParent()->getParent()->getSubtarget().getInstrInfo(); 696 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags()); 750 void MIPrinter::print(const MachineOperand &Op, cons argument 871 print(const MachineMemOperand &Op) argument [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeTypes.cpp | 491 SDValue Op = OrigOp; local 493 AnalyzeNewValue(Op); // Op may morph. 495 if (Op.getNode()->getNodeId() == Processed) 500 NewOps.push_back(Op); 501 } else if (Op != OrigOp) { 504 NewOps.push_back(Op); 750 void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) { argument 752 TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) && 756 SDValue &OpEntry = PromotedIntegers[Op]; 761 SetSoftenedFloat(SDValue Op, SDValue Result) argument 782 SetPromotedFloat(SDValue Op, SDValue Result) argument 793 SetScalarizedVector(SDValue Op, SDValue Result) argument 807 GetExpandedInteger(SDValue Op, SDValue &Lo, SDValue &Hi) argument 817 SetExpandedInteger(SDValue Op, SDValue Lo, SDValue Hi) argument 834 GetExpandedFloat(SDValue Op, SDValue &Lo, SDValue &Hi) argument 844 SetExpandedFloat(SDValue Op, SDValue Lo, SDValue Hi) argument 861 GetSplitVector(SDValue Op, SDValue &Lo, SDValue &Hi) argument 871 SetSplitVector(SDValue Op, SDValue Lo, SDValue Hi) argument 890 SetWidenedVector(SDValue Op, SDValue Result) argument 907 BitConvertToInteger(SDValue Op) argument 914 BitConvertVectorToIntegerVector(SDValue Op) argument 923 CreateStackStoreLoad(SDValue Op, EVT DestVT) argument 1065 SDValue Op = N->getOperand(0); local 1144 SplitInteger(SDValue Op, EVT LoVT, EVT HiVT, SDValue &Lo, SDValue &Hi) argument 1159 SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi) argument [all...] |
H A D | LegalizeTypesGeneric.cpp | 37 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); local 38 GetExpandedOp(Op, Lo, Hi); 325 void DAGTypeLegalizer::IntegerToVector(SDValue Op, unsigned NumElements, argument 328 assert(Op.getValueType().isInteger()); 329 SDLoc DL(Op); 334 SplitInteger(Op, Parts[0], Parts[1]); 340 Ops.push_back(DAG.getNode(ISD::BITCAST, DL, EltVT, Op)); 519 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); local 520 GetSplitOp(Op, Lo, Hi);
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H A D | ScheduleDAGFast.cpp | 230 for (const SDValue &Op : N->op_values()) { 231 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); 685 const SDValue &Op = N->getOperand(NumLeft-1); local 686 SDNode *OpN = Op.getNode(); 688 if (NumLeft == NumOps && Op.getValueType() == MVT::Glue) {
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/external/llvm/lib/Target/AMDGPU/InstPrinter/ |
H A D | AMDGPUInstPrinter.cpp | 373 const MCOperand &Op = MI->getOperand(OpNo); local 374 if (Op.isReg()) { 375 switch (Op.getReg()) { 381 printRegOperand(Op.getReg(), O, MRI); 384 } else if (Op.isImm()) { 390 printImmediate32(Op.getImm(), O); 392 printImmediate64(Op.getImm(), O); 396 printImmediate32(Op.getImm(), O); 401 O << formatDec(Op.getImm()); 403 } else if (Op 580 const MCOperand &Op = MI->getOperand(OpNo); local 591 const MCOperand &Op = MI->getOperand(OpNo); local 626 const MCOperand &Op = MI->getOperand(OpNo); local 680 const MCOperand &Op = MI->getOperand(OpNo); local [all...] |
/external/llvm/lib/Target/AMDGPU/ |
H A D | SIRegisterInfo.cpp | 375 static unsigned getNumSubRegsForSpillOp(unsigned Op) { argument 377 switch (Op) {
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEFrameLowering.cpp | 798 unsigned Op = 0; local 800 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO; 803 Op = (Reg == Mips::HI0) ? Mips::MFHI64 : Mips::MFLO64; 806 BuildMI(MBB, MI, DL, TII.get(Op), Mips::K0)
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/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 81 for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOWI, ISD::FPOW, 83 setOperationAction(Op, T, Expand); 86 for (auto Op : 88 setOperationAction(Op, T, Legal); 96 for (auto Op : 101 setOperationAction(Op, T, Expand); 120 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC}) 121 setOperationAction(Op, T, Expand); 526 SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op, argument 528 SDLoc DL(Op); 559 LowerCopyToReg(SDValue Op, SelectionDAG &DAG) const argument 586 LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const argument 592 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const argument 607 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const argument 621 LowerExternalSymbol( SDValue Op, SelectionDAG &DAG) const argument 638 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const argument 648 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const argument 674 LowerVASTART(SDValue Op, SelectionDAG &DAG) const argument [all...] |
H A D | WebAssemblyRegStackify.cpp | 434 static MachineInstr *MoveForSingleUse(unsigned Reg, MachineOperand& Op, argument 454 Op.setReg(NewReg); 462 LIS.getInstructionIndex(*Op.getParent()).getRegSlot(), 477 unsigned Reg, MachineOperand &Op, MachineInstr &Def, MachineBasicBlock &MBB, 482 DEBUG(dbgs() << " - for use in "; Op.getParent()->dump()); 486 Op.setReg(NewReg); 537 unsigned Reg, MachineOperand &Op, MachineInstr *Def, MachineBasicBlock &MBB, 555 Op.setReg(TeeReg); 601 MachineOperand &Op = *Range.begin(); local 608 return Op; 476 RematerializeCheapDef( unsigned Reg, MachineOperand &Op, MachineInstr &Def, MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator Insert, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI, const WebAssemblyInstrInfo *TII, const WebAssemblyRegisterInfo *TRI) argument 536 MoveAndTeeForMultiUse( unsigned Reg, MachineOperand &Op, MachineInstr *Def, MachineBasicBlock &MBB, MachineInstr *Insert, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI, const WebAssemblyInstrInfo *TII) argument 739 MachineOperand &Op = TreeWalker.Pop(); local [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmInstrumentation.cpp | 154 void AddBusyRegs(const X86Operand &Op) { argument 155 AddBusyReg(Op.getMemBaseReg()); 156 AddBusyReg(Op.getMemIndexReg()); 210 virtual void InstrumentMemOperandSmall(X86Operand &Op, unsigned AccessSize, 214 virtual void InstrumentMemOperandLarge(X86Operand &Op, unsigned AccessSize, 222 void InstrumentMemOperand(X86Operand &Op, unsigned AccessSize, bool IsWrite, 236 void EmitLEA(X86Operand &Op, unsigned Size, unsigned Reg, MCStreamer &Out) { argument 241 Op.addMemOperands(Inst, 5); 245 void ComputeMemOperandAddress(X86Operand &Op, unsigned Size, 251 std::unique_ptr<X86Operand> AddDisplacement(X86Operand &Op, 279 InstrumentMemOperand( X86Operand &Op, unsigned AccessSize, bool IsWrite, const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) argument 416 MCParsedAsmOperand &Op = *Operands[Ix]; local 431 ComputeMemOperandAddress(X86Operand &Op, unsigned Size, unsigned Reg, MCContext &Ctx, MCStreamer &Out) argument 466 AddDisplacement(X86Operand &Op, int64_t Displacement, MCContext &Ctx, int64_t *Residue) argument 616 InstrumentMemOperandSmall( X86Operand &Op, unsigned AccessSize, bool IsWrite, const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) argument 691 InstrumentMemOperandLarge( X86Operand &Op, unsigned AccessSize, bool IsWrite, const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) argument 887 InstrumentMemOperandSmall( X86Operand &Op, unsigned AccessSize, bool IsWrite, const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) argument 963 InstrumentMemOperandLarge( X86Operand &Op, unsigned AccessSize, bool IsWrite, const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) argument [all...] |
/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86AsmBackend.cpp | 143 unsigned Op = Inst.getOpcode(); local 144 switch (Op) { 146 return Op; 185 unsigned Op = Inst.getOpcode(); local 186 switch (Op) { 188 return Op;
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/external/llvm/lib/Transforms/IPO/ |
H A D | WholeProgramDevirt.cpp | 374 unsigned Op = GlobalSlotOffset / ElemSize; local 375 if (Op >= Init->getNumOperands()) 378 auto Fn = dyn_cast<Function>(Init->getOperand(Op)->stripPointerCasts());
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/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineLoadStoreAlloca.cpp | 790 Value *Op = LI.getOperand(0); local 798 Op, DL.getPrefTypeAlignment(LI.getType()), DL, &LI, AC, DT); 809 if (Instruction *NewGEPI = replaceGEPIdxWithZero(*this, Op, LI)) { 848 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(Op)) { 857 Constant::getNullValue(Op->getType()), &LI); 864 if (isa<UndefValue>(Op) || 865 (isa<ConstantPointerNull>(Op) && LI.getPointerAddressSpace() == 0)) { 870 Constant::getNullValue(Op->getType()), &LI); 874 if (Op->hasOneUse()) { 885 if (SelectInst *SI = dyn_cast<SelectInst>(Op)) { [all...] |
/external/llvm/lib/Transforms/Scalar/ |
H A D | DeadStoreElimination.cpp | 91 Value *Op = DeadInst->getOperand(op); local 95 if (!Op->use_empty()) continue; 97 if (Instruction *OpI = dyn_cast<Instruction>(Op))
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H A D | EarlyCSE.cpp | 644 Value *Op = getOrCreateResult(InVal.DefInst, Inst->getType()); local 645 if (Op != nullptr) { 649 Inst->replaceAllUsesWith(Op);
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H A D | LoopUnrollPass.cpp | 338 for (Value *Op : I->operands()) { 341 auto *OpI = dyn_cast<Instruction>(Op); 515 Value *Op = PN->getIncomingValueForBlock(ExitingBB); local 516 if (auto *OpI = dyn_cast<Instruction>(Op))
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/external/llvm/tools/llvm-bcanalyzer/ |
H A D | llvm-bcanalyzer.cpp | 642 const BitCodeAbbrevOp &Op = Abbv->getOperandInfo(i); local 643 if (!Op.isEncoding() || Op.getEncoding() != BitCodeAbbrevOp::Array)
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/external/llvm/tools/llvm-c-test/ |
H A D | echo.cpp | 326 LLVMOpcode Op = LLVMGetConstOpcode(Cst); local 327 switch(Op) { 332 fprintf(stderr, "%d is not a supported opcode\n", Op); 417 LLVMOpcode Op = LLVMGetInstructionOpcode(Src); local 418 switch(Op) { 655 fprintf(stderr, "%d is not a supported opcode\n", Op);
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/external/llvm/tools/llvm-stress/ |
H A D | llvm-stress.cpp | 345 Instruction::BinaryOps Op; variable 349 case 0:{Op = (isFloat?Instruction::FAdd : Instruction::Add); break; } 350 case 1:{Op = (isFloat?Instruction::FSub : Instruction::Sub); break; } 351 case 2:{Op = (isFloat?Instruction::FMul : Instruction::Mul); break; } 352 case 3:{Op = (isFloat?Instruction::FDiv : Instruction::SDiv); break; } 353 case 4:{Op = (isFloat?Instruction::FDiv : Instruction::UDiv); break; } 354 case 5:{Op = (isFloat?Instruction::FRem : Instruction::SRem); break; } 355 case 6:{Op = (isFloat?Instruction::FRem : Instruction::URem); break; } 356 case 7: {Op = Instruction::Shl; break; } 357 case 8: {Op [all...] |
/external/llvm/utils/TableGen/ |
H A D | CodeGenInstruction.h | 45 static ConstraintInfo getTied(unsigned Op) { argument 48 I.OtherTiedOperand = Op; 173 std::pair<unsigned,unsigned> ParseOperandName(const std::string &Op, 178 unsigned getFlattenedOperandNumber(std::pair<unsigned,unsigned> Op) const { 179 return OperandList[Op.first].MIOperandNo + Op.second; 184 std::pair<unsigned,unsigned> getSubOperandNumber(unsigned Op) const { 187 if (OperandList[i].MIOperandNo+OperandList[i].MINumOperands > Op) 188 return std::make_pair(i, Op-OperandList[i].MIOperandNo); 196 std::pair<unsigned,unsigned> Op local [all...] |
H A D | DAGISelMatcherGen.cpp | 680 Record *Op = N->getOperator(); local 682 CodeGenInstruction &II = CGT.getInstruction(Op); 709 Record *Op = N->getOperator(); local 711 CodeGenInstruction &II = CGT.getInstruction(Op); 712 const DAGInstruction &Inst = CGP.getInstruction(Op);
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/external/skqp/tools/ |
H A D | remote_demo.cpp | 82 class Op { class 84 explicit Op(const SkScalerContextRec& rec) : descriptor{rec} {} function in class:Op 109 Op* op = this->createOp(0, tf, rec); 113 op->~Op(); 119 Op* op = this->createOp(1, tf, rec); 124 op->~Op(); 130 Op* op = this->createOp(2, tf, rec); 134 memcpy(glyph.fImage, fBuffer + sizeof(Op), glyph.rowBytes() * glyph.fHeight); 135 op->~Op(); 141 Op* o [all...] |
/external/swiftshader/third_party/LLVM/examples/Kaleidoscope/Chapter3/ |
H A D | toy.cpp | 108 char Op; member in class:BinaryExprAST 112 : Op(op), LHS(lhs), RHS(rhs) {} 369 switch (Op) {
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