/external/swiftshader/third_party/LLVM/include/llvm/Analysis/ |
H A D | ConstantsScanner.h | 28 unsigned OpIdx; // Operand index member in class:llvm::constant_iterator 33 assert(!InstI.atEnd() && OpIdx < InstI->getNumOperands() && 35 return isa<Constant>(InstI->getOperand(OpIdx)); 39 inline constant_iterator(const Function *F) : InstI(inst_begin(F)), OpIdx(0) { 47 : InstI(inst_end(F)), OpIdx(0) { 50 inline bool operator==(const _Self& x) const { return OpIdx == x.OpIdx && 56 return cast<Constant>(InstI->getOperand(OpIdx)); 61 ++OpIdx; 64 while (OpIdx < NumOperand [all...] |
/external/llvm/utils/TableGen/ |
H A D | CodeEmitterGen.cpp | 86 unsigned OpIdx; local 87 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { 89 OpIdx = CGI.Operands[OpIdx].MIOperandNo; 90 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && 113 OpIdx = NumberedOp++; 116 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx); 127 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); 133 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")"; 192 unsigned OpIdx; local [all...] |
H A D | CodeGenInstruction.cpp | 140 unsigned OpIdx; local 141 if (hasOperandNamed(Name, OpIdx)) return OpIdx; 147 /// given name. If so, return true and set OpIdx to the index of the 149 bool CGIOperandList::hasOperandNamed(StringRef Name, unsigned &OpIdx) const { 153 OpIdx = i; 176 unsigned OpIdx = getOperandNamed(OpName); local 180 if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp && 186 return std::make_pair(OpIdx, 0U); 190 DagInit *MIOpInfo = OperandList[OpIdx] [all...] |
H A D | AsmWriterEmitter.cpp | 613 void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) { argument 614 assert(OpIdx >= 0 && OpIdx < 0xFE && "Idx out of range"); 617 OpMap[Op] = std::make_pair(OpIdx, PrintMethodIdx); 1023 O << " int OpIdx = AsmString[I++] - 1;\n"; 1025 O << " printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, "; 1047 << " const MCInst *MI, unsigned OpIdx,\n" 1061 << " " << PrintMethods[i] << "(MI, OpIdx, "
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | ProcessImplicitDefs.cpp | 49 unsigned Reg, unsigned OpIdx, 51 switch(OpIdx) { 263 unsigned OpIdx = Ops[j]; local 264 RMI->RemoveOperand(OpIdx-j); 48 CanTurnIntoImplicitDef(MachineInstr *MI, unsigned Reg, unsigned OpIdx, SmallSet<unsigned, 8> &ImpDefRegs) argument
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H A D | DwarfEHPrepare.cpp | 190 unsigned OpIdx = Sel->getNumArgOperands() - 1; local 191 GlobalVariable *GV = dyn_cast<GlobalVariable>(Sel->getArgOperand(OpIdx)); 193 Sel->setArgOperand(OpIdx, EHCatchAllValue->getInitializer());
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H A D | MachineInstr.cpp | 829 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, argument 832 assert(OpIdx < getNumOperands() && "OpIdx out of range"); 835 if (OpIdx < InlineAsm::MIOp_FirstOperand) 847 if (i + NumOps > OpIdx) { 858 MachineInstr::getRegClassConstraint(unsigned OpIdx, 863 return TII->getRegClass(getDesc(), OpIdx, TRI); 865 if (!getOperand(OpIdx).isReg()) 870 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, 1600 unsigned OpIdx = DeadOps.back(); local 1652 unsigned OpIdx = DeadOps.back(); local [all...] |
H A D | MachineLICM.cpp | 230 unsigned Reg, unsigned OpIdx, 669 unsigned Reg, unsigned OpIdx, 668 getRegisterClassIDAndCost(const MachineInstr *MI, unsigned Reg, unsigned OpIdx, unsigned &RCId, unsigned &RCCost) const argument
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/external/swiftshader/third_party/LLVM/utils/TableGen/ |
H A D | CodeEmitterGen.cpp | 107 unsigned OpIdx; local 108 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { 110 OpIdx = CGI.Operands[OpIdx].MIOperandNo; 111 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && 118 OpIdx = NumberedOp++; 121 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx); 132 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); 139 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
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H A D | CodeGenInstruction.cpp | 135 unsigned OpIdx; local 136 if (hasOperandNamed(Name, OpIdx)) return OpIdx; 142 /// given name. If so, return true and set OpIdx to the index of the 144 bool CGIOperandList::hasOperandNamed(StringRef Name, unsigned &OpIdx) const { 148 OpIdx = i; 171 unsigned OpIdx = getOperandNamed(OpName); local 175 if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp && 181 return std::make_pair(OpIdx, 0U); 185 DagInit *MIOpInfo = OperandList[OpIdx] [all...] |
/external/llvm/lib/CodeGen/ |
H A D | ExecutionDepsFix.cpp | 206 bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref); 478 bool ExeDepsFix::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, argument 480 unsigned reg = MI->getOperand(OpIdx).getReg(); 566 unsigned OpIdx = UndefReads.back().second; local 573 if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg())) 574 TII->breakPartialRegDependency(*UndefMI, OpIdx, TRI); 581 OpIdx = UndefReads.back().second;
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64AddressTypePromotion.cpp | 208 static bool shouldSExtOperand(const Instruction *Inst, int OpIdx) { argument 209 return !(isa<SelectInst>(Inst) && OpIdx == 0); 311 for (int OpIdx = 0, EndOpIdx = Inst->getNumOperands(); OpIdx != EndOpIdx; 312 ++OpIdx) { 313 DEBUG(dbgs() << "Operand:\n" << *(Inst->getOperand(OpIdx)) << '\n'); 314 if (Inst->getOperand(OpIdx)->getType() == SExt->getType() || 315 !shouldSExtOperand(Inst, OpIdx)) { 320 Value *Opnd = Inst->getOperand(OpIdx); 323 Inst->setOperand(OpIdx, ConstantIn [all...] |
H A D | AArch64PromoteConstant.cpp | 245 /// Check if the given use (Instruction + OpIdx) of Cst should be converted into 251 unsigned OpIdx) { 254 if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2) 258 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0) 262 if (isa<const InsertValueInst>(Instr) && OpIdx > 1) 265 if (isa<const AllocaInst>(Instr) && OpIdx > 0) 269 if (isa<const LoadInst>(Instr) && OpIdx > 0) 273 if (isa<const StoreInst>(Instr) && OpIdx > 1) 277 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0) 250 shouldConvertUse(const Constant *Cst, const Instruction *Instr, unsigned OpIdx) argument
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/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCCodeEmitter.cpp | 62 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx, 68 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 74 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, 80 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 86 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx, 93 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx, 99 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 105 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 111 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, 116 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx, 197 getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 218 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 244 getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 271 getCondBranchTargetOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 293 getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 313 getMemExtendOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 322 getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 341 getTestBranchTargetOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 363 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 391 getVecShifterOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 415 getFixedPointScaleOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 424 getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 433 getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 442 getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 451 getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 460 getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 469 getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 478 getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 487 getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 497 getMoveVecShifterOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument [all...] |
/external/llvm/lib/Target/AMDGPU/ |
H A D | R600ExpandSpecialInstrs.cpp | 60 int OpIdx = TII->getOperandIdx(*OldMI, Op); local 61 if (OpIdx > -1) { 62 uint64_t Val = OldMI->getOperand(OpIdx).getImm();
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H A D | AMDGPUOpenCLImageTypeLoweringPass.cpp | 120 GetArgMD(MDNode *KernelMDNode, unsigned OpIdx) { argument 124 Res.push_back(Node->getOperand(OpIdx));
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/external/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | RegBankSelect.h | 320 unsigned OpIdx; member in class:llvm::RegBankSelect::RepairingPlacement 332 /// Create a repairing placement for the \p OpIdx-th operand of 337 RepairingPlacement(MachineInstr &MI, unsigned OpIdx, 344 unsigned getOpIdx() const { return OpIdx; }
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/external/llvm/include/llvm/CodeGen/ |
H A D | ScheduleDAGInstrs.h | 58 /// For non-data-dependent uses, OpIdx == -1. 61 int OpIdx; member in struct:llvm::PhysRegSUOper 64 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
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/external/llvm/lib/CodeGen/GlobalISel/ |
H A D | RegisterBankInfo.cpp | 186 const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, 190 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI); 223 for (unsigned OpIdx = 0, End = MI.getNumOperands(); OpIdx != End; ++OpIdx) { 224 const MachineOperand &MO = MI.getOperand(OpIdx); 243 CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, TRI); 273 Mapping.setOperandMapping(OpIdx, RegSize, *CurRegBank); 288 for (unsigned OpIdx = 0, End = MI.getNumOperands(); OpIdx ! 185 getRegBankFromConstraints( const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) const argument 453 setOperandMapping( unsigned OpIdx, unsigned MaskSize, const RegisterBank &RegBank) argument 525 getVRegsMem(unsigned OpIdx) argument 561 createVRegs(unsigned OpIdx) argument [all...] |
H A D | RegBankSelect.cpp | 365 for (unsigned OpIdx = 0, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx; 366 ++OpIdx) { 367 const MachineOperand &MO = MI.getOperand(OpIdx); 373 DEBUG(dbgs() << "Opd" << OpIdx); 375 InstrMapping.getOperandMapping(OpIdx); 384 RepairPts.emplace_back(RepairingPlacement(MI, OpIdx, *TRI, *this, 391 RepairingPlacement(MI, OpIdx, *TRI, *this, RepairingPlacement::Insert)); 482 unsigned OpIdx = RepairPt.getOpIdx(); local 483 MachineOperand &MO = MI.getOperand(OpIdx); 567 RepairingPlacement( MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo &TRI, Pass &P, RepairingPlacement::RepairingKind Kind) argument [all...] |
/external/capstone/arch/PowerPC/ |
H A D | PPCInstPrinter.c | 41 static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, 748 int OpIdx, PrintMethodIdx; local 982 OpIdx = *c - 1; 985 printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 419 unsigned OpIdx = 0; local 421 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 422 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 433 MIB.addOperand(MI.getOperand(OpIdx++)); 436 MIB.addOperand(MI.getOperand(OpIdx++)); 437 MIB.addOperand(MI.getOperand(OpIdx++)); 440 MIB.addOperand(MI.getOperand(OpIdx++)); 447 SrcOpIdx = OpIdx++; 450 MIB.addOperand(MI.getOperand(OpIdx++)); 451 MIB.addOperand(MI.getOperand(OpIdx 483 unsigned OpIdx = 0; local 532 unsigned OpIdx = 0; local 613 unsigned OpIdx = 0; local 977 unsigned OpIdx = 0; local 1007 unsigned OpIdx = 0; local 1038 unsigned OpIdx = 0; local [all...] |
/external/llvm/lib/ExecutionEngine/RuntimeDyld/ |
H A D | RuntimeDyldChecker.cpp | 256 unsigned OpIdx = OpIdxExpr.getValue(); local 257 if (OpIdx >= Inst.getNumOperands()) { 260 ErrMsgStream << "Invalid operand index '" << format("%i", OpIdx) 269 const MCOperand &Op = Inst.getOperand(OpIdx); 273 ErrMsgStream << "Operand '" << format("%i", OpIdx) << "' of instruction '"
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/external/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 403 unsigned OpIdx = 0; local 405 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 406 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 418 MIB.addOperand(MI.getOperand(OpIdx++)); 421 MIB.addOperand(MI.getOperand(OpIdx++)); 422 MIB.addOperand(MI.getOperand(OpIdx++)); 425 MIB.addOperand(MI.getOperand(OpIdx++)); 432 SrcOpIdx = OpIdx++; 435 MIB.addOperand(MI.getOperand(OpIdx++)); 436 MIB.addOperand(MI.getOperand(OpIdx 468 unsigned OpIdx = 0; local 522 unsigned OpIdx = 0; local 605 unsigned OpIdx = 0; local 1383 unsigned OpIdx = 0; local 1414 unsigned OpIdx = 0; local [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 81 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 85 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, 92 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 98 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 103 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 108 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 113 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 125 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 131 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 191 getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 551 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 580 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) argument 618 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 631 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 643 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 655 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 667 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 696 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 710 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 726 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 741 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 753 getThumbBranchTargetOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 783 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 824 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 844 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 857 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &, const MCSubtargetInfo &STI) const argument 872 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 924 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 956 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 997 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1010 getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1066 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1100 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1123 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1135 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1155 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1192 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1208 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1223 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1234 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1274 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1313 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 1361 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument [all...] |