| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64AddressTypePromotion.cpp | 167 const Instruction *Opnd = cast<Instruction>(Inst->getOperand(0)); local
170 Opnd->getOperand(0)->getType()->getIntegerBitWidth() &&
320 Value *Opnd = Inst->getOperand(OpIdx); local
321 if (const ConstantInt *Cst = dyn_cast<ConstantInt>(Opnd)) {
328 if (isa<UndefValue>(Opnd)) {
338 SExtForOpnd->setOperand(0, Opnd);
|
| /external/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 44 addOperand(MCInst &Inst, const MCOperand& Opnd) { argument
45 Inst.addOperand(Opnd);
46 return Opnd.isValid() ?
|
| /external/llvm/lib/Transforms/Scalar/ |
| H A D | ConstantHoisting.cpp | 123 Value *Opnd = Inst->getOperand(Idx); local
124 if (auto CastInst = dyn_cast<Instruction>(Opnd))
240 Value *Opnd = Inst->getOperand(Idx); local
243 if (auto ConstInt = dyn_cast<ConstantInt>(Opnd)) {
249 if (auto CastInst = dyn_cast<Instruction>(Opnd)) {
264 if (auto ConstExpr = dyn_cast<ConstantExpr>(Opnd)) {
490 Value *Opnd = ConstUser.Inst->getOperand(ConstUser.OpndIdx); local
493 if (isa<ConstantInt>(Opnd)) {
502 if (auto CastInst = dyn_cast<Instruction>(Opnd)) {
524 if (auto ConstExpr = dyn_cast<ConstantExpr>(Opnd)) {
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAddSub.cpp | 702 for (const FAddend *Opnd : Opnds) {
704 Value *V = createAddendVal(*Opnd, NeedNeg);
793 for (const FAddend *Opnd : Opnds) {
794 if (Opnd->isConstant())
797 const FAddendCoef &CE = Opnd->getCoef();
820 Value *FAddCombine::createAddendVal(const FAddend &Opnd, bool &NeedNeg) { argument
821 const FAddendCoef &Coeff = Opnd.getCoef();
823 if (Opnd.isConstant()) {
828 Value *OpndVal = Opnd.getSymVal();
|
| /external/swiftshader/third_party/subzero/src/ |
| H A D | IceAssemblerMIPS32.cpp | 143 bool encodeOperand(const Operand *Opnd, IValueT &Value, argument
146 if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
|
| H A D | IceCfg.cpp | 640 auto *Opnd = Instr.getSrc(i); local
641 if (auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
659 auto *Opnd = Instr.getSrc(i); local
660 if (auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
|
| H A D | IceCfgNode.cpp | 366 const Operand *Opnd) {
367 if (Var1 == Opnd)
369 const auto *Var2 = llvm::dyn_cast<Variable>(Opnd);
365 sameVarOrReg(TargetLowering *Target, const Variable *Var1, const Operand *Opnd) argument
|
| H A D | IceInstX86Base.h | 243 static void validateVectorAddrModeOpnd(const Operand *Opnd) { argument
244 if (llvm::isa<X86OperandMem>(Opnd) && isVectorType(Opnd->getType())) {
|
| H A D | IceTargetLoweringX86BaseImpl.h | 146 const Inst *getProducerFor(const Operand *Opnd) const;
322 const Inst *BoolFolding<Traits>::getProducerFor(const Operand *Opnd) const {
323 auto *Var = llvm::dyn_cast<const Variable>(Opnd);
793 inline uint64_t getConstantMemoryOrder(Operand *Opnd) { argument
794 if (auto *Integer = llvm::dyn_cast<ConstantInteger32>(Opnd))
3503 inline bool isZero(const Operand *Opnd) { argument
3504 if (auto *C64 = llvm::dyn_cast<ConstantInteger64>(Opnd))
3506 if (auto *C32 = llvm::dyn_cast<ConstantInteger32>(Opnd))
5940 void TargetX86Base<TraitsType>::doMockBoundsCheck(Operand *Opnd) {
5943 if (auto *Mem = llvm::dyn_cast<X86OperandMem>(Opnd)) {
[all...] |
| H A D | IceTargetLoweringMIPS32.cpp | 258 inline uint64_t getConstantMemoryOrder(Operand *Opnd) { argument
259 if (auto *Integer = llvm::dyn_cast<ConstantInteger32>(Opnd))
|
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 1335 SDValue Opnd = Op->getOperand(++OpNo), In64; local
1337 if (Opnd.getValueType() == MVT::i64)
1338 In64 = initAccumulator(Opnd, DL, DAG);
1340 Ops.push_back(Opnd);
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 2232 const Value *Opnd = nullptr; local
2235 case CmpInst::FCMP_FALSE: Opnd = I->getOperand(2); break;
2236 case CmpInst::FCMP_TRUE: Opnd = I->getOperand(1); break;
2239 if (Opnd) {
2240 unsigned OpReg = getRegForValue(Opnd);
2243 bool OpIsKill = hasTrivialKill(Opnd);
|
| /external/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 2299 /// \brief Build a truncate instruction of \p Opnd producing a \p Ty
2301 /// trunc Opnd to Ty.
2302 TruncBuilder(Instruction *Opnd, Type *Ty) : TypePromotionAction(Opnd) { argument
2303 IRBuilder<> Builder(Opnd);
2304 Val = Builder.CreateTrunc(Opnd, Ty, "promoted");
2323 /// \brief Build a sign extension instruction of \p Opnd producing a \p Ty
2325 /// sext Opnd to Ty.
2326 SExtBuilder(Instruction *InsertPt, Value *Opnd, Type *Ty) argument
2329 Val = Builder.CreateSExt(Opnd, T
2351 ZExtBuilder(Instruction *InsertPt, Value *Opnd, Type *Ty) argument
2530 createTrunc(Instruction *Opnd, Type *Ty) argument
2538 createSExt(Instruction *Inst, Value *Opnd, Type *Ty) argument
2546 createZExt(Instruction *Inst, Value *Opnd, Type *Ty) argument
3062 Value *Opnd = ExtOpnd->getOperand(OpIdx); local
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 1601 MCOperand Opnd; local
1614 Opnd = Inst.getOperand(1);
1615 if (!Opnd.isImm())
1617 Imm = Opnd.getImm();
1631 Opnd = Inst.getOperand(2);
1632 if (!Opnd.isImm())
1634 Imm = Opnd.getImm();
1782 MCOperand Opnd; local
1789 Opnd = Inst.getOperand(0);
1790 if (!Opnd
1871 MCOperand Opnd = Inst.getOperand(1); local
[all...] |