Searched defs:Rd (Results 1 - 12 of 12) sorted by relevance

/external/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp159 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, argument
161 if (Rd == Ra)
166 if (TRI->isPhysicalRegister(Rd) || TRI->isPhysicalRegister(Ra)) {
167 DEBUG(dbgs() << "Rd is a physical reg:" << TRI->isPhysicalRegister(Rd)
174 PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd);
187 const LiveInterval &ld = LIs.getInterval(Rd);
243 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, argument
249 if (Rd != Ra) {
251 << PrintReg(Rd, TR
363 unsigned Rd = MI.getOperand(0).getReg(); local
373 unsigned Rd = MI.getOperand(0).getReg(); local
[all...]
/external/mesa3d/src/mesa/swrast/
H A Ds_blend.c486 const GLfloat Rd = dest[i][RCOMP]; local
508 sR = Rd;
513 sR = 1.0F - Rd;
670 dR = Rd;
675 dR = 1.0F - Rd;
740 r = Rs * sR + Rd * dR;
746 r = Rs * sR - Rd * dR;
752 r = Rd * dR - Rs * sR;
758 r = MIN2( Rd, Rs );
763 r = MAX2( Rd, R
[all...]
/external/capstone/arch/AArch64/
H A DAArch64Disassembler.c738 unsigned Rd = fieldFromInstruction(Insn, 0, 5); local
743 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
746 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
843 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
872 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
893 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
907 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
921 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
926 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1398 unsigned Rd, R local
1458 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
1491 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
1531 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
1549 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
1567 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
[all...]
/external/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp652 unsigned Rd = fieldFromInstruction(Insn, 0, 5); local
657 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
660 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
743 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
771 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
792 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
805 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
817 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
822 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1296 unsigned Rd local
1353 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
1384 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
1423 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
1440 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
1459 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1789 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); local
1798 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1800 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1813 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local
1821 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1823 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1839 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); local
1848 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1959 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local
1960 Rd |
2208 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local
2458 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local
2497 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local
2533 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local
2568 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local
2621 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local
2666 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local
2709 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local
3260 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local
3392 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local
3451 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local
3509 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local
3576 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local
3640 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local
3710 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local
3774 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local
3848 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local
[all...]
/external/swiftshader/third_party/subzero/src/
H A DIceAssemblerMIPS32.cpp271 const IValueT Rd = encodeGPRegister(OpRd, "Rd", InsnName); local
275 Opcode |= Rd << 11;
284 const IValueT Rd = encodeGPRegister(OpRd, "Rd", InsnName); local
290 Opcode |= Rd << 11;
527 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "clz"); local
529 Opcode |= Rd << 11;
530 Opcode |= Rd << 1
657 const IValueT Rd = local
772 IValueT Rd = encodeGPRegister(OpRd, "Rd", "mfhi"); local
779 IValueT Rd = encodeGPRegister(OpRd, "Rd", "mflo"); local
819 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "pseudo-move"); local
836 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "movf"); local
871 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "movt"); local
[all...]
/external/vixl/src/aarch64/
H A Dassembler-aarch64.h2584 static Instr Rd(CPURegister rd) { function in class:vixl::aarch64::Assembler
/external/capstone/arch/ARM/
H A DARMDisassembler.c1891 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
1899 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2096 unsigned Rd = fieldFromInstruction_4(Insn, 8, 4); local
2105 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2107 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2120 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
2128 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2131 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2147 unsigned Rd = fieldFromInstruction_4(Insn, 16, 4); local
2156 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Addres
2289 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
2623 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
2895 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
2943 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
2992 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
3028 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
3081 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
3127 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
3175 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
4134 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
4268 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
4334 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
4398 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
4463 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
4524 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
4592 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
4653 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
4732 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); local
[all...]
/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1844 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
1852 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2070 unsigned Rd = fieldFromInstruction(Insn, 8, 4); local
2079 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2081 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2094 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
2102 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2105 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2121 unsigned Rd = fieldFromInstruction(Insn, 16, 4); local
2130 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Addres
2334 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
2659 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
2930 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
2977 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3025 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3060 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3113 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3158 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3201 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4252 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4382 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4449 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4515 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4582 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4646 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4716 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4780 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4861 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp115 // Rd = ALLOCA Rs, A
117 // Rd - address of the allocated space
2187 // Rd = alloca Rs, #A
2189 // If Rs and Rd are different registers, use this sequence:
2190 // Rd = sub(r29, Rs)
2192 // Rd = and(Rd, #-A) ; if necessary
2194 // Rd = add(Rd, #CF) ; CF size aligned to at most A
2196 // Rd
2203 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); local
[all...]
H A DHexagonInstrInfo.cpp1238 unsigned Rd = Op0.getReg(); local
1246 if (Rd != Rs)
1247 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1248 .addReg(Pu, (Rd == Rt) ? K1 : 0)
1250 if (Rd != Rt)
1251 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
3340 // Rd = Rs
3347 // Rd = #u6
3377 // Rd=#U6 ; jump #r9:2
3378 // Rd
[all...]
/external/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1903 MCOperand &Rd = Inst.getOperand(0); local
1926 TmpInst.addOperand(Rd);
1940 if (Value == 0) { // convert to $Rd = $Rs
1942 MCOperand &Rd = Inst.getOperand(0); local
1944 TmpInst.addOperand(Rd);
1952 MCOperand &Rd = Inst.getOperand(0); local
1954 TmpInst.addOperand(Rd);
2150 MCOperand &Rd = Inst.getOperand(0); local
2153 TmpInst.addOperand(Rd);

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