/external/swiftshader/third_party/subzero/src/ |
H A D | IceRegistersMIPS32.h | 68 static inline GPRRegister getEncodedGPR(RegNumT RegNum) { argument 69 assert(int(Reg_GPR_First) <= int(RegNum)); 70 assert(unsigned(RegNum) <= Reg_GPR_Last); 71 return GPRRegister(RegNum - Reg_GPR_First); 74 static inline bool isGPRReg(RegNumT RegNum) { argument 75 bool IsGPR = ((int(Reg_GPR_First) <= int(RegNum)) && 76 (unsigned(RegNum) <= Reg_GPR_Last)) || 77 ((int(Reg_I64PAIR_First) <= int(RegNum)) && 78 (unsigned(RegNum) <= Reg_I64PAIR_Last)); 82 static inline FPRRegister getEncodedFPR(RegNumT RegNum) { argument 88 isFPRReg(RegNumT RegNum) argument 93 getEncodedFPR64(RegNumT RegNum) argument 99 isFPR64Reg(RegNumT RegNum) argument 106 get64PairFirstRegNum(RegNumT RegNum) argument 119 get64PairSecondRegNum(RegNumT RegNum) argument [all...] |
H A D | IceInstX8632.cpp | 105 const auto RegNum = Var->getRegNum(); local 106 if (RegNum == Target->getFrameReg()) { 108 } else if (RegNum != Target->getStackReg()) {
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H A D | IceInstX8664.cpp | 95 const auto RegNum = Var->getRegNum(); local 96 if (RegNum == Target->getFrameReg()) { 98 } else if (RegNum != Target->getStackReg()) {
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H A D | IceRegistersARM32.h | 105 static inline void assertValidRegNum(RegNumT RegNum) { argument 106 (void)RegNum; 107 assert(RegNum.hasValue()); 110 static inline bool isGPRegister(RegNumT RegNum) { argument 111 RegNum.assertIsValid(); 112 return RegTable[RegNum].IsGPR; 125 static inline GPRRegister getEncodedGPR(RegNumT RegNum) { argument 126 RegNum.assertIsValid(); 127 return GPRRegister(RegTable[RegNum].Encoding); 140 static inline bool isGPR(RegNumT RegNum) { argument 145 getI64PairFirstGPRNum(RegNumT RegNum) argument 150 getI64PairSecondGPRNum(RegNumT RegNum) argument 155 isI64RegisterPair(RegNumT RegNum) argument 160 isEncodedSReg(RegNumT RegNum) argument 175 getEncodedSReg(RegNumT RegNum) argument 180 isEncodedDReg(RegNumT RegNum) argument 195 getEncodedDReg(RegNumT RegNum) argument 200 isEncodedQReg(RegNumT RegNum) argument 205 getEncodedQReg(RegNumT RegNum) argument 210 getRegName(RegNumT RegNum) argument [all...] |
H A D | IceRegAlloc.cpp | 434 const RegNumT RegNum = *RegNumBVIter(Iter.RegMask).begin(); local 435 Iter.Cur->setRegNumTmp(RegNum); 436 Variable *Preg = Target->getPhysicalRegister(RegNum, Iter.Cur->getType()); 621 const auto RegNum = Cur->getRegNum(); local 623 assert(Cur->getRegNumTmp() == RegNum); 626 const auto &Aliases = *RegAliases[RegNum]; 648 const RegNumT RegNum = local 650 Iter.Cur->setRegNumTmp(RegNum); 655 const auto &Aliases = *RegAliases[RegNum]; 741 const auto RegNum local 802 const auto RegNum = Item->getRegNumTmp(); local 916 const RegNumT RegNum = Item->getRegNumTmp(); local [all...] |
H A D | IceTargetLoweringX8664.cpp | 324 const auto RegNum = Var->getRegNum(); local 325 if ((RegNum == Traits::RegisterSet::Reg_rsp) || 326 (RegNum == Traits::RegisterSet::Reg_rbp)) { 439 RegNumT RegNum, RegNum32; local 442 RegNum = Traits::getGprForType(IceType_i64, T->getRegNum()); 443 RegNum32 = Traits::getGprForType(IceType_i32, RegNum); 446 assert(RegNum != Traits::RegisterSet::Reg_rsp); 447 assert(RegNum != Traits::RegisterSet::Reg_rbp); 459 Variable *T64 = makeReg(IceType_i64, RegNum); 487 T = makeReg(IceType_i64, RegNum); [all...] |
H A D | IceTargetLowering.cpp | 135 for (RegNumT RegNum : RegNumBVIter(Bitset)) { 144 Str << getRegName(RegNum); 185 const auto RegNum = RegNumT::fromInt(RegIndex); local 186 RegNameToIndex[getRegName(RegNum)] = RegNum;
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/external/llvm/lib/CodeGen/ |
H A D | StackMaps.cpp | 79 int RegNum = TRI->getDwarfRegNum(Reg, false); local 80 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNum < 0; ++SR) 81 RegNum = TRI->getDwarfRegNum(*SR, false); 83 assert(RegNum >= 0 && "Invalid Dwarf register number."); 84 return (unsigned)RegNum; 450 /// uint16 : Dwarf RegNum 456 /// uint16 : Dwarf RegNum
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
H A D | MBlazeAsmPrinter.cpp | 139 unsigned RegNum = getMBlazeRegisterNumbering(Reg); local 141 CPUBitmask |= (1 << RegNum);
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
H A D | MipsAsmPrinter.cpp | 141 unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg); local 143 FPUBitmask |= (3 << RegNum); 149 FPUBitmask |= (1 << RegNum); 156 unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg); local 157 CPUBitmask |= (1 << RegNum);
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/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 1042 unsigned RegNum = (IsExtReg ? (1 << 7) : 0); local 1043 RegNum |= GetX86RegNum(MO) << 4; 1044 EmitImmediate(MCOperand::CreateImm(RegNum), 1, FK_Data_1, CurByte, OS,
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | RegAllocBasic.cpp | 267 unsigned RegNum = I->first; local 269 if (TargetRegisterInfo::isPhysicalRegister(RegNum)) 270 PhysReg2LiveUnion[RegNum].unify(VirtReg);
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86RegisterInfo.cpp | 80 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const { argument 81 switch (getLLVMRegNum(RegNum, isEH)) {
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/AsmParser/ |
H A D | MBlazeAsmParser.cpp | 92 unsigned RegNum; member in struct:__anon22863::MBlazeOperand::__anon22864::__anon22866 143 return Reg.RegNum; 230 static MBlazeOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { argument 232 Op->Reg.RegNum = RegNum;
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/external/llvm/lib/Target/ARM/ |
H A D | ARMLoadStoreOptimizer.cpp | 1008 unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg); local 1012 if (RegNum <= PRegNum) 1017 else if (!isNotVFP && RegNum != PRegNum+1) 1036 PRegNum = RegNum;
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/external/llvm/lib/Target/Lanai/AsmParser/ |
H A D | LanaiAsmParser.cpp | 51 bool ParseRegister(unsigned &RegNum, SMLoc &StartLoc, SMLoc &EndLoc) override; 106 unsigned RegNum; member in struct:llvm::__anon14393::LanaiOperand::RegOp 141 return Reg.RegNum; 576 static std::unique_ptr<LanaiOperand> createReg(unsigned RegNum, SMLoc Start, argument 579 Op->Reg.RegNum = RegNum; 675 unsigned RegNum; local 680 RegNum = MatchRegisterName(Lexer.getTok().getIdentifier()); 681 if (RegNum == 0) 684 return LanaiOperand::createReg(RegNum, Star 689 ParseRegister(unsigned &RegNum, SMLoc &StartLoc, SMLoc &EndLoc) argument [all...] |
/external/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 2177 unsigned RegNum; 2185 RegNum = RegLst & 0xf; 2188 if (RegNum > 9) 2191 for (unsigned i = 0; i < RegNum; i++) 2214 unsigned RegNum = RegLst & 0x3; local 2216 for (unsigned i = 0; i <= RegNum; i++)
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/external/llvm/lib/Target/Mips/ |
H A D | MipsAsmPrinter.cpp | 265 unsigned RegNum = TRI->getEncodingValue(Reg); local 270 FPUBitmask |= (1 << RegNum); 273 FPUBitmask |= (3 << RegNum); 277 CPUBitmask |= (1 << RegNum);
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/external/llvm/lib/Target/Sparc/AsmParser/ |
H A D | SparcAsmParser.cpp | 202 unsigned RegNum; member in struct:__anon14494::SparcOperand::RegOp 256 return Reg.RegNum; 350 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, argument 353 Op->Reg.RegNum = RegNum; 383 Op.Reg.RegNum = IntPairRegs[regIdx / 2]; 394 Op.Reg.RegNum = DoubleRegs[regIdx / 2]; 417 Op.Reg.RegNum = Reg; 430 Op.Reg.RegNum = CoprocPairRegs[regIdx / 2];
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMCodeEmitter.cpp | 1293 unsigned RegNum = getARMRegisterNumbering(MO.getReg()); local 1295 RegNum < 16); 1296 Binary |= 0x1 << RegNum;
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/external/capstone/arch/ARM/ |
H A D | ARMInstPrinter.c | 1768 unsigned RegNum; local 1780 RegNum = MCOperand_getReg(MO2); 1781 if (RegNum) { 1783 printRegName(MI->csh, O, RegNum); 1785 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = RegNum;
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/external/clang/include/clang/Basic/ |
H A D | TargetInfo.h | 765 const unsigned RegNum; member in struct:clang::TargetInfo::AddlRegName
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/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDILCFGStructurizer.cpp | 237 int RegNum, const DebugLoc &DL); 502 int RegNum, const DebugLoc &DL) { 507 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false); 500 insertCondBranchBefore( MachineBasicBlock *blk, MachineBasicBlock::iterator I, int NewOpcode, int RegNum, const DebugLoc &DL) argument
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXAsmPrinter.cpp | 304 unsigned RegNum = RegMap[Reg]; local 326 Ret |= (RegNum & 0x0FFFFFFF);
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/external/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.cpp | 1353 unsigned RegNum = Reg.EnumValue; local 1354 if (AllocatableRegs.count(RegNum)) 1357 UberSetIDs.join(0, RegNum);
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