Searched defs:Rm (Results 1 - 14 of 14) sorted by relevance

/external/vogar/src/vogar/commands/
H A DRm.java25 public final class Rm { class
28 public Rm(Log log) { method in class:Rm
/external/swiftshader/third_party/subzero/src/
H A DIceAssemblerX86Base.h845 // for Reg and Rm because they could be of different types (e.g., in
846 // mov[sz]x instructions.) If Addr is not nullptr, then Rm is ignored, and
852 const RmType Rm,
864 : (Rm & 0x08) ? T::Operand::RexB : T::Operand::RexNone;
869 (Addr == nullptr && is8BitRegisterRequiringRex(TyRm, Rm))) {
882 void emitRexRB(const Type Ty, const RegType Reg, const RmType Rm) { argument
883 assembleAndEmitRex(Ty, Reg, Ty, Rm);
888 const RmType Rm) {
889 assembleAndEmitRex(TyReg, Reg, TyRm, Rm);
895 template <typename RmType> void emitRexB(const Type Ty, const RmType Rm) { argument
851 assembleAndEmitRex(const Type TyReg, const RegType Reg, const Type TyRm, const RmType Rm, const typename T::Address *Addr = nullptr) argument
887 emitRexRB(const Type TyReg, const RegType Reg, const Type TyRm, const RmType Rm) argument
[all...]
/external/capstone/arch/AArch64/
H A DAArch64Disassembler.c845 unsigned Rm = fieldFromInstruction(insn, 16, 5); local
874 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
895 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1398 unsigned Rd, Rn, Rm; local
1407 Rm = fieldFromInstruction(insn, 16, 5);
1416 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1422 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1428 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1434 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1440 DecodeGPR64RegisterClass(Inst, Rm, Add
[all...]
/external/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp745 unsigned Rm = fieldFromInstruction(insn, 16, 5); local
773 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
794 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1298 unsigned Rm = fieldFromInstruction(insn, 16, 5); local
1312 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1318 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1324 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1330 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1336 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1342 DecodeGPR64RegisterClass(Inst, Rm, Add
[all...]
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp860 // [Rn, Rm]
861 // {5-3} = Rm
866 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); local
867 return (Rm << 3) | Rn;
1073 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); local
1086 // {3-0} = Rm
1090 uint32_t Binary = Rm;
1103 // {13} 1 == imm12, 0 == Rm
1105 // {11-0} imm12/Rm
1112 // if reg +/- reg, Rm wil
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp687 // [Rn, Rm]
688 // {5-3} = Rm
693 unsigned Rm = getARMRegisterNumbering(MO2.getReg()); local
694 return (Rm << 3) | Rn;
897 unsigned Rm = getARMRegisterNumbering(MO1.getReg()); local
906 // {3-0} = Rm
910 uint32_t Binary = Rm;
923 // {13} 1 == imm12, 0 == Rm
925 // {11-0} imm12/Rm
936 // {13} 1 == imm12, 0 == Rm
[all...]
/external/v8/src/arm/
H A Ddisasm-arm.cc91 void FormatNeonMemory(int Rn, int align, int Rm);
317 } else if (format[1] == 'm') { // 'rm: Rm register
418 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) { argument
425 if (Rm == 15) {
427 } else if (Rm == 13) {
431 "], r%d", Rm);
739 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
745 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
757 // The order of registers is: <RdLo>, <RdHi>, <Rm>, <Rs>
2292 int Rm local
2305 int Rm = instr->VmValue(); local
[all...]
H A Dsimulator-arm.cc2122 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
5281 int Rm = instr->VmValue(); local
5310 if (Rm != 15) {
5311 if (Rm == 13) {
5314 set_register(Rn, get_register(Rn) + get_register(Rm));
5322 int Rm = instr->VmValue(); local
5351 if (Rm != 15) {
5352 if (Rm == 13) {
5355 set_register(Rn, get_register(Rn) + get_register(Rm));
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1023 unsigned Rm = fieldFromInstruction32(Val, 0, 4); local
1028 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1060 unsigned Rm = fieldFromInstruction32(Val, 0, 4); local
1065 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1342 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
1404 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1444 unsigned Rm = fieldFromInstruction32(Val, 0, 4); local
1467 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1486 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
1578 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1841 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); local
1942 unsigned Rm = fieldFromInstruction32(Val, 0, 4); local
1964 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
2213 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
2461 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
2500 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
2536 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
2571 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
2668 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
2713 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
2783 unsigned Rm = fieldFromInstruction32(Val, 3, 3); local
2830 unsigned Rm = fieldFromInstruction32(Val, 2, 4); local
3050 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); local
3075 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
3109 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
3318 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
3391 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
3450 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
3508 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
3575 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
3639 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
3709 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
3773 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
3847 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
3912 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
3938 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local
[all...]
/external/vixl/src/aarch64/
H A Dassembler-aarch64.h2594 static Instr Rm(CPURegister rm) { function in class:vixl::aarch64::Assembler
2602 return Rm(rm);
/external/capstone/arch/ARM/
H A DARMDisassembler.c1165 unsigned Rm = fieldFromInstruction_4(Val, 0, 4); local
1170 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1204 unsigned Rm = fieldFromInstruction_4(Val, 0, 4); local
1209 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1520 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); local
1582 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1626 unsigned Rm = fieldFromInstruction_4(Val, 0, 4); local
1652 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1670 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); local
1703 if (type && Rm
1892 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); local
2149 unsigned Rm = fieldFromInstruction_4(Insn, 8, 4); local
2271 unsigned Rm = fieldFromInstruction_4(Val, 0, 4); local
2288 unsigned wb, Rn, Rm; local
2622 unsigned wb, Rn, Rm; local
2894 unsigned Rn, Rm, align, size; local
2942 unsigned Rn, Rm, align, size; local
2991 unsigned Rn, Rm, inc; local
3027 unsigned Rn, Rm, size, inc, align; local
3126 unsigned Rm, size; local
3174 unsigned Rn, Rm, op; local
3259 unsigned Rm = fieldFromInstruction_4(Val, 3, 3); local
3310 unsigned Rm = fieldFromInstruction_4(Val, 2, 4); local
3844 unsigned Rm = fieldFromInstruction_2(Insn, 3, 4); local
3871 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); local
3919 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); local
4185 unsigned pred, Rm; local
4267 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); local
4333 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); local
4397 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); local
4462 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); local
4523 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); local
4591 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); local
4652 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); local
4731 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); local
4801 unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); local
4828 unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); local
5068 unsigned Rm = fieldFromInstruction_4(Val, 0, 4); local
[all...]
/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1140 unsigned Rm = fieldFromInstruction(Val, 0, 4); local
1145 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1177 unsigned Rm = fieldFromInstruction(Val, 0, 4); local
1182 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1477 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
1539 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1581 unsigned Rm = fieldFromInstruction(Val, 0, 4); local
1607 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1626 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
1659 if (type && Rm
1845 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
2123 unsigned Rm = fieldFromInstruction(Insn, 8, 4); local
2151 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
2317 unsigned Rm = fieldFromInstruction(Val, 0, 4); local
2339 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
2664 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
2933 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
2980 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
3028 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
3063 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
3160 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
3205 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
3286 unsigned Rm = fieldFromInstruction(Val, 3, 3); local
3333 unsigned Rm = fieldFromInstruction(Val, 2, 4); local
3909 unsigned Rm = fieldFromInstruction(Insn, 3, 4); local
3934 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
3989 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4308 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4381 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4448 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4514 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4581 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4645 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4715 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4779 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4860 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4932 unsigned Rm = fieldFromInstruction(Insn, 5, 1); local
4958 unsigned Rm = fieldFromInstruction(Insn, 5, 1); local
5247 unsigned Rm = fieldFromInstruction(Val, 0, 4); local
[all...]
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp2821 unsigned Rm = MI.getOperand(3).getReg(); local
2822 return (Rt == Rm) ? 4 : 3;
2828 unsigned Rm = MI.getOperand(3).getReg(); local
2829 if (Rt == Rm)
2858 unsigned Rm = MI.getOperand(3).getReg(); local
2859 if (!Rm)
2861 if (Rt == Rm)
2870 unsigned Rm = MI.getOperand(3).getReg(); local
2871 return (Rt == Rm) ? 3 : 2;
2889 unsigned Rm local
2909 unsigned Rm = MI.getOperand(3).getReg(); local
2917 unsigned Rm = MI.getOperand(3).getReg(); local
2935 unsigned Rm = MI.getOperand(4).getReg(); local
2949 unsigned Rm = MI.getOperand(4).getReg(); local
[all...]
/external/conscrypt/benchmark-android/
H A Dvogar.jarMETA-INF/ META-INF/MANIFEST.MF vogar/ vogar/TestProperties.class TestProperties.java package vogar ...

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