Searched defs:Rn (Results 1 - 16 of 16) sorted by relevance

/external/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp438 unsigned Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); local
443 assert(isARMLowRegister(Rn));
451 .addReg(Rn, RegState::Define)
452 .addReg(Rn)
H A DARMBaseInstrInfo.cpp2908 unsigned Rn = MI.getOperand(2).getReg(); local
2913 return (Rt == Rn) ? 3 : 2;
2934 unsigned Rn = MI.getOperand(3).getReg(); local
2939 return (Rt == Rn) ? 4 : 3;
2944 unsigned Rn = MI.getOperand(3).getReg(); local
2945 return (Rt == Rn) ? 4 : 3;
2981 unsigned Rn = MI.getOperand(2).getReg(); local
2982 return (Rt == Rn) ? 3 : 2;
/external/swiftshader/third_party/subzero/src/
H A DIceAssemblerARM32.cpp135 IValueT encodeGPRRegister(RegARM32::GPRRegister Rn) { argument
136 return static_cast<IValueT>(Rn);
283 // Value=0000000pu0w0nnnn0000iiiiiiiiiiii where nnnn is the base register Rn,
285 // Rn should be used, and iiiiiiiiiiii defines the rotated Imm8 value.
289 // Value=00000000pu0w0nnnn0000iiii0000jjjj where nnnn=Rn, iiiijjjj=Imm8, p=1
291 // Rn.
295 // Value=0000000pu0w0nnnn0000iiiiiiiiiiii where nnnn is the base register Rn,
297 // Rn should be used, and iiiiiiiiiiii defines the immediate 12-bit value.
301 // Value=000000001000nnnn0000000000000000 where nnnn=Rn.
304 // Value=0000000pu0w00nnnnttttiiiiiss0mmmm where nnnn is the base register Rn,
[all...]
/external/capstone/arch/AArch64/
H A DAArch64Disassembler.c739 unsigned Rn = fieldFromInstruction(Insn, 5, 5); local
744 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
747 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
844 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
873 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
894 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
944 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
993 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1008 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
1066 DecodeGPR64spRegisterClass(Inst, Rn, Add
1194 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
1270 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
1398 unsigned Rd, Rn, Rm; local
1459 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
1568 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
[all...]
/external/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp653 unsigned Rn = fieldFromInstruction(Insn, 5, 5); local
658 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
661 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
744 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
772 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
793 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
839 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
890 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
900 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
958 DecodeGPR64spRegisterClass(Inst, Rn, Add
1085 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
1168 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
1297 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
1354 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
1460 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
[all...]
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp860 // [Rn, Rm]
862 // {2-0} = Rn
865 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); local
867 return (Rm << 3) | Rn;
883 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
967 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1072 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); local
1083 // {16-13} = Rn
1091 Binary |= Rn << 13;
1159 // {12-9} Rn
1169 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. local
1179 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); local
1216 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); local
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp687 // [Rn, Rm]
689 // {2-0} = Rn
692 unsigned Rn = getARMRegisterNumbering(MO1.getReg()); local
694 return (Rm << 3) | Rn;
709 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
788 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
896 unsigned Rn = getARMRegisterNumbering(MO.getReg()); local
903 // {16-13} = Rn
911 Binary |= Rn << 13;
922 // {17-14} Rn
927 unsigned Rn = getARMRegisterNumbering(MO.getReg()); local
996 unsigned Rn = getARMRegisterNumbering(MO.getReg()); local
1031 unsigned Rn = getARMRegisterNumbering(MO.getReg()); local
[all...]
/external/v8/src/arm/
H A Ddisasm-arm.cc91 void FormatNeonMemory(int Rn, int align, int Rm);
305 if (format[1] == 'n') { // 'rn: Rn register
418 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) { argument
420 "[r%d", Rn);
734 // Rn field to encode it.
739 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
740 // Rn field to encode the Rd register and the Rd field to encode
741 // the Rn register.
745 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
746 // Rn fiel
2288 int Rn = instr->VnValue(); local
2301 int Rn = instr->VnValue(); local
2318 int Rn = instr->Bits(19, 16); local
[all...]
H A Dsimulator-arm.cc2109 // Rn field to encode it.
2122 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
2123 // Rn field to encode the Rd register and the Rd field to encode
2124 // the Rn register.
2138 // when referring to the target registers. They are mapped to the Rn
2141 // RdHi == Rn (This is confusingly stored in variable rd here
2143 // Rn field to encode the Rd register. Good luck figuring
5279 int Rn = instr->VnValue(); local
5282 int32_t address = get_register(Rn);
5312 set_register(Rn, addres
5320 int Rn = instr->VnValue(); local
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1117 // Writeback not allowed if Rn is in the target list.
1189 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
1234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1340 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
1359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1400 if (writeback && (Rn == 15 || Rn == Rt))
1443 unsigned Rn local
1485 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
1595 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
1625 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
1840 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); local
1869 unsigned Rn = fieldFromInstruction32(Val, 13, 4); local
1887 unsigned Rn = fieldFromInstruction32(Val, 9, 4); local
1962 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
2211 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
2460 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
2499 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
2535 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
2570 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
2711 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
2782 unsigned Rn = fieldFromInstruction32(Val, 0, 3); local
2797 unsigned Rn = fieldFromInstruction32(Val, 0, 3); local
2829 unsigned Rn = fieldFromInstruction32(Val, 6, 4); local
2858 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
2910 unsigned Rn = fieldFromInstruction32(Val, 9, 4); local
2925 unsigned Rn = fieldFromInstruction32(Val, 8, 4); local
2953 unsigned Rn = fieldFromInstruction32(Val, 9, 4); local
2985 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
3014 unsigned Rn = fieldFromInstruction32(Val, 13, 4); local
3108 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
3238 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
3262 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
3287 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
3312 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
3340 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
3365 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
3390 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
3449 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
3507 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
3574 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
3638 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
3708 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
3772 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
3846 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
3992 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
4029 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); local
[all...]
/external/vixl/src/aarch64/
H A Dassembler-aarch64.h2589 static Instr Rn(CPURegister rn) { function in class:vixl::aarch64::Assembler
/external/capstone/arch/ARM/
H A DARMDisassembler.c1268 // Writeback not allowed if Rn is in the target list.
1375 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
1420 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1518 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
1538 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1558 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1565 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1578 if (writeback && (Rn == 15 || Rn == Rt))
1625 unsigned Rn local
1669 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
1861 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
1893 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
1915 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
2148 unsigned Rn = fieldFromInstruction_4(Insn, 0, 4); local
2178 unsigned Rn = fieldFromInstruction_4(Val, 13, 4); local
2197 unsigned Rn = fieldFromInstruction_4(Val, 9, 4); local
2288 unsigned wb, Rn, Rm; local
2622 unsigned wb, Rn, Rm; local
2894 unsigned Rn, Rm, align, size; local
2942 unsigned Rn, Rm, align, size; local
2991 unsigned Rn, Rm, inc; local
3027 unsigned Rn, Rm, size, inc, align; local
3174 unsigned Rn, Rm, op; local
3258 unsigned Rn = fieldFromInstruction_4(Val, 0, 3); local
3274 unsigned Rn = fieldFromInstruction_4(Val, 0, 3); local
3309 unsigned Rn = fieldFromInstruction_4(Val, 6, 4); local
3339 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
3410 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
3475 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
3541 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
3642 unsigned Rn = fieldFromInstruction_4(Val, 9, 4); local
3658 unsigned Rn = fieldFromInstruction_4(Val, 8, 4); local
3687 unsigned Rn = fieldFromInstruction_4(Val, 9, 4); local
3735 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
3796 unsigned Rn = fieldFromInstruction_4(Val, 13, 4); local
3918 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
4113 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
4136 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
4160 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
4186 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
4214 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
4240 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
4266 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
4332 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
4396 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
4461 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
4522 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
4590 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
4651 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
4730 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
4876 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
4913 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
4976 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); local
5066 unsigned Rn = fieldFromInstruction_4(Val, 16, 4); local
[all...]
/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1236 // Writeback not allowed if Rn is in the target list.
1329 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
1379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1475 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
1494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1521 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1535 if (writeback && (Rn == 15 || Rn == Rt))
1580 unsigned Rn local
1625 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
1815 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
1846 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
1868 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
2122 unsigned Rn = fieldFromInstruction(Insn, 0, 4); local
2150 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
2200 unsigned Rn = fieldFromInstruction(Val, 13, 4); local
2218 unsigned Rn = fieldFromInstruction(Val, 9, 4); local
2238 unsigned Rn = fieldFromInstruction(Val, 9, 4); local
2337 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
2662 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
2932 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
2979 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3027 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3062 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3203 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3285 unsigned Rn = fieldFromInstruction(Val, 0, 3); local
3300 unsigned Rn = fieldFromInstruction(Val, 0, 3); local
3332 unsigned Rn = fieldFromInstruction(Val, 6, 4); local
3361 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3442 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3526 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3606 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3712 unsigned Rn = fieldFromInstruction(Val, 9, 4); local
3727 unsigned Rn = fieldFromInstruction(Val, 8, 4); local
3755 unsigned Rn = fieldFromInstruction(Val, 9, 4); local
3802 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3862 unsigned Rn = fieldFromInstruction(Val, 13, 4); local
3988 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4232 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4254 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4277 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4302 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4330 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4355 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4380 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4447 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4513 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4580 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4644 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4714 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4778 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4859 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
5005 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
5042 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
5100 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
5245 unsigned Rn = fieldFromInstruction(Val, 16, 4); local
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp4090 unsigned Rn = Inst.getOperand(0).getReg(); local
4095 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
4157 TmpInst.addOperand(Inst.getOperand(1)); // Rn
4222 unsigned Rn = Inst.getOperand(0).getReg(); local
4227 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
4245 unsigned Rn = Inst.getOperand(0).getReg(); local
4247 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
/external/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp3451 unsigned Rn = Inst.getOperand(3).getReg(); local
3452 if (RI->isSubRegisterEq(Rn, Rt))
3455 if (RI->isSubRegisterEq(Rn, Rt2))
3497 unsigned Rn = Inst.getOperand(3).getReg(); local
3498 if (RI->isSubRegisterEq(Rn, Rt))
3501 if (RI->isSubRegisterEq(Rn, Rt2))
3529 unsigned Rn = Inst.getOperand(2).getReg(); local
3530 if (RI->isSubRegisterEq(Rn, Rt))
3548 unsigned Rn = Inst.getOperand(2).getReg(); local
3549 if (RI->isSubRegisterEq(Rn, R
[all...]
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp4761 // If we have a three-operand form, make sure to set Rn to be the operand
6245 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); local
6248 if (Rn == Rt || Rn == Rt2)
6304 // Rt must be different from Rn.
6306 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); local
6308 if (Rt == Rn)
6327 // Rt must be different from Rn.
6329 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); local
6331 if (Rt == Rn)
6354 unsigned Rn = Inst.getOperand(0).getReg(); local
8449 unsigned Rn = Inst.getOperand(0).getReg(); local
8473 unsigned Rn = Inst.getOperand(0).getReg(); local
[all...]

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