Searched defs:getRegClass (Results 1 - 10 of 10) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/Target/ |
| H A D | TargetInstrInfo.cpp | 31 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, function in class:TargetInstrInfo
45 return TRI->getRegClass(RegClass);
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| H A D | MachineRegisterInfo.h | 209 /// getRegClass - Return the register class of the specified virtual register.
211 const TargetRegisterClass *getRegClass(unsigned Reg) const { function in class:llvm::MachineRegisterInfo
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineRegisterInfo.h | 196 return shouldTrackSubRegLiveness(*getRegClass(VReg));
526 /// constrainRegClass(ToReg, getRegClass(FromReg))
574 const TargetRegisterClass *getRegClass(unsigned Reg) const { function in class:llvm::MachineRegisterInfo
590 /// the select pass, using getRegClass is safe.
1032 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| H A D | TargetRegisterInfo.h | 455 /// getRegClass - Returns the register class associated with the enumeration
457 const TargetRegisterClass *getRegClass(unsigned i) const { function in class:llvm::TargetRegisterInfo
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 585 CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) { function in class:CodeGenRegBank
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| /external/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 45 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, function in class:TargetInstrInfo
60 return TRI->getRegClass(RegClass);
419 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
424 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
475 MF.getRegInfo().getRegClass(MO.getReg());
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| /external/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 1063 CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) { function in class:CodeGenRegBank
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| /external/swiftshader/third_party/subzero/src/ |
| H A D | IceOperand.h | 785 RegClass getRegClass() const { return RegisterClass; } function in class:Ice::RegNumT::Variable
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.cpp | 1809 SpillRCs.insert(MRI.getRegClass(VR));
1885 auto getRegClass = [&MRI,&HRI] (HexagonBlockRanges::RegisterRef R) local
1890 auto *RCR = MRI.getRegClass(R.Reg);
1953 RC = getRegClass({DataOp.getReg(), DataOp.getSubReg()});
1956 RC = getRegClass({DataOp.getReg(), DataOp.getSubReg()});
2112 auto *RC = getRegClass({SrcOp.getReg(), SrcOp.getSubReg()});
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 247 return isReg() && Reg.TRI->getRegClass(RCID).contains(getReg());
741 static int getRegClass(RegisterKind Is, unsigned RegWidth) { function
932 int RCID = getRegClass(RegKind, RegWidth);
935 const MCRegisterClass RC = TRI->getRegClass(RCID);
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