Searched defs:level_info (Results 1 - 4 of 4) sorted by relevance

/external/mesa3d/src/amd/vulkan/
H A Dradv_device.c1591 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip]; local
1598 va += level_info->offset;
1615 pitch_tile_max = level_info->nblk_x / 8 - 1;
1616 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
1699 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
1731 const struct radeon_surf_level *level_info = &iview->image->surface.level[level]; local
1836 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
1837 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
1838 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info
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/external/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_state.c2510 const struct radeon_surf_level *level_info; local
2526 level_info = &tex->surface.level[cb->base.u.tex.level];
2546 pitch_tile_max = level_info->nblk_x / 8 - 1;
2547 slice_tile_max = level_info->nblk_x *
2548 level_info->nblk_y / 64 - 1;
2551 cb_color_base = (tex->resource.gpu_address + level_info->offset) >> 8;
/external/libvpx/libvpx/vp9/encoder/
H A Dvp9_encoder.c550 static void init_level_info(Vp9LevelInfo *level_info) { argument
551 Vp9LevelStats *const level_stats = &level_info->level_stats;
552 Vp9LevelSpec *const level_spec = &level_info->level_spec;
2069 init_level_info(&cpi->level_info);
4861 Vp9LevelInfo *const level_info = &cpi->level_info; local
4862 Vp9LevelSpec *const level_spec = &level_info->level_spec;
4863 Vp9LevelStats *const level_stats = &level_info->level_stats;
H A Dvp9_encoder.h693 Vp9LevelInfo level_info; member in struct:VP9_COMP

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