/external/webrtc/webrtc/system_wrappers/include/ |
H A D | asm_defines.h | 59 .macro streqh reg1, reg2, num 60 strheq \reg1, \reg2, \num variable
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64PBQPRegAlloc.cpp | 150 bool haveSameParity(unsigned reg1, unsigned reg2) { argument 151 assert(isFPReg(reg1) && "Expecting an FP register for reg1"); 154 return isOdd(reg1) == isOdd(reg2);
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/external/v8/src/interpreter/ |
H A D | bytecode-register.cc | 107 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, argument 109 if (reg1.index() + 1 != reg2.index()) {
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/external/libyuv/files/source/ |
H A D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 99 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); 110 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); 121 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); 137 res8 = (v16u8)__msa_ilvr_w((v4i32)reg5, (v4i32)reg1); 138 res9 = (v16u8)__msa_ilvl_w((v4i32)reg5, (v4i32)reg1); 166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 180 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); 191 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); 202 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg [all...] |
H A D | scale_msa.cc | 70 v8u16 reg0, reg1, reg2, reg3; local 83 reg1 = __msa_hadd_u_h(vec1, vec1); 87 reg1 += reg3; 89 reg1 = (v8u16)__msa_srari_h((v8i16)reg1, 2); 90 dst0 = (v16u8)__msa_pckev_b((v16i8)reg1, (v16i8)reg0); 133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 158 reg1 = __msa_hadd_u_h(vec1, vec1); 162 reg5 = (v8u16)__msa_pckev_d((v2i64)reg3, (v2i64)reg1); 164 reg7 = (v8u16)__msa_pckod_d((v2i64)reg3, (v2i64)reg1); 296 v4u32 reg0, reg1, reg2, reg3; local [all...] |
/external/tensorflow/tensorflow/contrib/lite/ |
H A D | model_test.cc | 183 const TfLiteRegistration& reg1 = node_and_reg1->second; local 192 ASSERT_EQ(reg1, dummy_reg);
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/external/capstone/arch/X86/ |
H A D | X86Mapping.c | 47236 x86_reg reg1, reg2; member in struct:insn_reg2 47505 bool X86_insn_reg_intel2(unsigned int id, x86_reg *reg1, x86_reg *reg2) argument 47511 *reg1 = insn_regs_intel2[i].reg1; 47522 bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, x86_reg *reg2) argument 47529 *reg1 = insn_regs_intel2[i].reg2; 47530 *reg2 = insn_regs_intel2[i].reg1;
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/external/libvpx/libvpx/vpx_dsp/mips/ |
H A D | idct32x32_msa.c | 44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); 50 DOTP_CONST_PAIR(reg1, reg7, cospi_28_64, cospi_4_64, reg1, reg7); 52 BUTTERFLY_4(reg1, reg7, reg3, reg5, vec1, vec3, vec2, vec0); 65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); 69 DOTP_CONST_PAIR(reg6, reg1, cospi_6_64, cospi_26_64, reg6, reg1); 75 reg2 = reg1 + reg5; 76 reg1 128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 354 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 434 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local [all...] |
H A D | idct16x16_msa.c | 16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; local 19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); 23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1, 40 DOTP_CONST_PAIR(reg1, reg15, cospi_30_64, cospi_2_64, reg1, reg15); 43 reg9 = reg1 - loc2; 44 reg1 = reg1 + loc2; 57 loc1 = reg1 110 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; local [all...] |
/external/mesa3d/src/gallium/drivers/ilo/shader/ |
H A D | toy_legalize_ra.c | 82 const int *reg1 = elem1; local 86 return (*reg2 - *reg1);
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/external/vixl/test/aarch64/ |
H A D | test-utils-aarch64.cc | 197 const Register& reg1) { 198 VIXL_ASSERT(reg0.Is64Bits() && reg1.Is64Bits()); 200 int64_t result = core->xreg(reg1.GetCode()); 195 Equal64(const Register& reg0, const RegisterDump* core, const Register& reg1) argument
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/external/aac/libFDK/include/ |
H A D | fixpoint_math.h | 296 FIXP_DBL reg1, reg2; local 319 reg1 = invSqrtTab[index] + (fMultDiv2(diff, Fract) << 1); 321 /* reg1 = t[i] + (t[i+1]-t[i])*fract ... already computed ... 327 reg1 = fMultAddDiv2(reg1, Fract, diff); 341 reg1 = fMultDiv2(reg1, reg2) << 2; 346 return (reg1);
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/external/mesa3d/src/util/ |
H A D | register_allocate.c | 234 struct ra_reg *reg1 = ®s->regs[r1]; local 236 if (reg1->conflict_list) { 237 if (reg1->conflict_list_size == reg1->num_conflicts) { 238 reg1->conflict_list_size *= 2; 239 reg1->conflict_list = reralloc(regs->regs, reg1->conflict_list, 240 unsigned int, reg1->conflict_list_size); 242 reg1->conflict_list[reg1 [all...] |
/external/vixl/src/aarch32/ |
H A D | macro-assembler-aarch32.cc | 447 CPURegister reg1, 461 PushRegister(reg1); 467 (reg2.GetType() << 4) | reg1.GetType(); 472 reg2.GetRegSizeInBytes() + reg1.GetRegSizeInBytes(); 486 if (reg1.GetType() == CPURegister::kRRegister) { 487 available_registers.Remove(Register(reg1.GetCode())); 509 PushRegister(reg1); 516 PreparePrintfArgument(reg1, &core_count, &vfp_count, &printf_type); 446 Printf(const char* format, CPURegister reg1, CPURegister reg2, CPURegister reg3, CPURegister reg4) argument
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | RenderMachineFunction.cpp | 173 unsigned reg1, reg2; local 174 if ((iss >> reg1 >> std::ws)) { 176 intervalNumsToRender.insert(std::make_pair(reg1, reg1 + 1)); 181 intervalNumsToRender.insert(std::make_pair(reg1, reg2 + 1));
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/external/v8/src/arm64/ |
H A D | assembler-arm64.h | 347 Register GetAllocatableRegisterThatIsNotOneOf(Register reg1, 355 bool AreAliased(const CPURegister& reg1, 367 // arguments. At least one argument (reg1) must be valid (not NoCPUReg). 368 bool AreSameSizeAndType(const CPURegister& reg1, 387 explicit CPURegList(CPURegister reg1, argument 391 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()), 392 size_(reg1.SizeInBits()), type_(reg1.type()) { 393 DCHECK(AreSameSizeAndType(reg1, reg2, reg3, reg4));
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/external/swiftshader/third_party/subzero/src/ |
H A D | IceAssemblerX86BaseImpl.h | 2576 GPRRegister reg1) { 2581 emitRexRB(Ty, reg0, reg1); 2586 emitRegisterOperand(gprEncoding(reg0), gprEncoding(reg1)); 2648 GPRRegister reg1) { 2649 arith_int<7>(Ty, reg0, reg1); 2671 void AssemblerX86Base<TraitsType>::test(Type Ty, GPRRegister reg1, 2676 emitRexRB(Ty, reg1, reg2); 2681 emitRegisterOperand(gprEncoding(reg1), gprEncoding(reg2)); 3749 GPRRegister reg1) { 3755 emitRexB(Ty, reg1); 3748 xchg(Type Ty, GPRRegister reg0, GPRRegister reg1) argument [all...] |
/external/syslinux/gpxe/src/drivers/net/ |
H A D | sky2.c | 596 u32 reg1; local 599 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 600 reg1 &= ~phy_power[port]; 603 reg1 |= coma_mode[port]; 605 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 617 u32 reg1; local 662 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 663 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */ 664 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
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/external/v8/src/arm/ |
H A D | macro-assembler-arm.cc | 215 void MacroAssembler::Swap(Register reg1, argument 220 eor(reg1, reg1, Operand(reg2), LeaveCC, cond); 221 eor(reg2, reg2, Operand(reg1), LeaveCC, cond); 222 eor(reg1, reg1, Operand(reg2), LeaveCC, cond); 224 mov(scratch, reg1, LeaveCC, cond); 225 mov(reg1, reg2, LeaveCC, cond); 2840 void MacroAssembler::JumpIfNotBothSmi(Register reg1, argument 2844 tst(reg1, Operan 2857 JumpIfEitherSmi(Register reg1, Register reg2, Label* on_either_smi) argument 3709 GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6) argument 3735 AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6, Register reg7, Register reg8) argument [all...] |
/external/v8/src/compiler/mips/ |
H A D | code-generator-mips.cc | 916 Register reg1 = kScratchReg; local 927 __ li(reg1, 0x1F); 928 __ Subu(i.OutputRegister(), reg1, reg2); 936 Register reg1 = kScratchReg; local 946 __ srl(reg1, i.InputRegister(0), 1); 948 __ And(reg1, reg1, at); 949 __ addu(reg1, reg1, reg2); 953 __ srl(reg2, reg1, [all...] |
/external/v8/src/compiler/mips64/ |
H A D | code-generator-mips64.cc | 1040 Register reg1 = kScratchReg; local 1051 __ li(reg1, 0x1F); 1052 __ Subu(i.OutputRegister(), reg1, reg2); 1060 Register reg1 = kScratchReg; local 1071 __ li(reg1, 0x3F); 1072 __ Subu(i.OutputRegister(), reg1, reg2); 1080 Register reg1 = kScratchReg; local 1090 __ dsrl(reg1, i.InputRegister(0), 1); 1092 __ And(reg1, reg1, a 1124 Register reg1 = kScratchReg; local [all...] |
/external/v8/src/full-codegen/arm/ |
H A D | full-codegen-arm.cc | 1519 void FullCodeGenerator::PushOperands(Register reg1, Register reg2) { argument 1521 __ Push(reg1, reg2); 1524 void FullCodeGenerator::PopOperands(Register reg1, Register reg2) { argument 1526 __ Pop(reg1, reg2);
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/external/v8/src/full-codegen/arm64/ |
H A D | full-codegen-arm64.cc | 66 void EmitJumpIfEitherNotSmi(Register reg1, Register reg2, Label* target) { argument 69 __ Orr(temp, reg1, reg2); 2691 void FullCodeGenerator::PushOperands(Register reg1, Register reg2) { argument 2693 __ Push(reg1, reg2); 2696 void FullCodeGenerator::PushOperands(Register reg1, Register reg2, argument 2699 __ Push(reg1, reg2, reg3); 2702 void FullCodeGenerator::PopOperands(Register reg1, Register reg2) { argument 2704 __ Pop(reg1, reg2);
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/external/v8/src/full-codegen/mips/ |
H A D | full-codegen-mips.cc | 1522 void FullCodeGenerator::PushOperands(Register reg1, Register reg2) { argument 1524 __ Push(reg1, reg2); 1527 void FullCodeGenerator::PushOperands(Register reg1, Register reg2, argument 1530 __ Push(reg1, reg2, reg3); 1533 void FullCodeGenerator::PushOperands(Register reg1, Register reg2, argument 1536 __ Push(reg1, reg2, reg3, reg4); 1539 void FullCodeGenerator::PopOperands(Register reg1, Register reg2) { argument 1541 __ Pop(reg1, reg2);
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/external/v8/src/full-codegen/mips64/ |
H A D | full-codegen-mips64.cc | 1524 void FullCodeGenerator::PushOperands(Register reg1, Register reg2) { argument 1526 __ Push(reg1, reg2); 1529 void FullCodeGenerator::PushOperands(Register reg1, Register reg2, argument 1532 __ Push(reg1, reg2, reg3); 1535 void FullCodeGenerator::PushOperands(Register reg1, Register reg2, argument 1538 __ Push(reg1, reg2, reg3, reg4); 1541 void FullCodeGenerator::PopOperands(Register reg1, Register reg2) { argument 1543 __ Pop(reg1, reg2);
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