Searched defs:reg3 (Results 1 - 24 of 24) sorted by relevance

/external/v8/src/interpreter/
H A Dbytecode-register.cc107 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, argument
112 if (reg3.is_valid() && reg2.index() + 1 != reg3.index()) {
115 if (reg4.is_valid() && reg3.index() + 1 != reg4.index()) {
/external/libyuv/files/source/
H A Drotate_msa.cc85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
99 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3);
111 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7);
121 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3);
147 res8 = (v16u8)__msa_ilvr_w((v4i32)reg7, (v4i32)reg3);
148 res9 = (v16u8)__msa_ilvl_w((v4i32)reg7, (v4i32)reg3);
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
180 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3);
192 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7);
202 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3);
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H A Dscale_msa.cc70 v8u16 reg0, reg1, reg2, reg3; local
85 reg3 = __msa_hadd_u_h(vec3, vec3);
87 reg1 += reg3;
133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
160 reg3 = __msa_hadd_u_h(vec3, vec3);
162 reg5 = (v8u16)__msa_pckev_d((v2i64)reg3, (v2i64)reg1);
164 reg7 = (v8u16)__msa_pckod_d((v2i64)reg3, (v2i64)reg1);
296 v4u32 reg0, reg1, reg2, reg3; local
334 reg3 = __msa_hadd_u_w(vec3, vec3);
338 reg3
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H A Drow_msa.cc481 v16u8 reg0, reg1, reg2, reg3; local
508 reg3 = (v16u8)__msa_pckev_b((v16i8)vec5, (v16i8)vec2);
510 dst0 = (v16u8)__msa_vshf_b(shuffler0, (v16i8)reg3, (v16i8)reg0);
511 dst1 = (v16u8)__msa_vshf_b(shuffler1, (v16i8)reg3, (v16i8)reg1);
512 dst2 = (v16u8)__msa_vshf_b(shuffler2, (v16i8)reg3, (v16i8)reg2);
774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
793 reg3 = (v8u16)__msa_ilvev_b(zero, (v16i8)vec3);
799 reg3 *= const_0x81;
803 reg1 += reg3;
826 v8u16 reg0, reg1, reg2, reg3, reg local
1085 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; local
1159 v4u32 reg0, reg1, reg2, reg3; local
1237 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
1373 v4u32 reg0, reg1, reg2, reg3, rgba_scale; local
1506 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6; local
1553 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
1648 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
1705 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
1767 v16u8 src0, src1, src2, reg0, reg1, reg2, reg3, dst0; local
1808 v16u8 src0, src1, src2, reg0, reg1, reg2, reg3, dst0; local
1856 v8u16 src0, src1, src2, src3, reg0, reg1, reg2, reg3; local
1937 v8u16 src0, src1, src2, src3, reg0, reg1, reg2, reg3; local
2020 v8i16 reg0, reg1, reg2, reg3; local
2125 v8i16 reg0, reg1, reg2, reg3; local
2666 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; local
2729 v4i32 reg0, reg1, reg2, reg3; local
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/external/libvpx/libvpx/vpx_dsp/mips/
H A Didct32x32_msa.c44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
51 DOTP_CONST_PAIR(reg5, reg3, cospi_12_64, cospi_20_64, reg5, reg3);
52 BUTTERFLY_4(reg1, reg7, reg3, reg5, vec1, vec3, vec2, vec0);
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
67 DOTP_CONST_PAIR(reg4, reg3, cospi_14_64, cospi_18_64, reg4, reg3);
77 reg5 = reg7 + reg3;
78 reg7 = reg7 - reg3;
128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
354 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
434 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
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H A Didct16x16_msa.c16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1,
24 reg2, reg3, reg4, reg5, reg6, reg7);
49 DOTP_CONST_PAIR(reg13, reg3, cospi_6_64, cospi_26_64, loc0, loc1);
50 BUTTERFLY_4(loc0, loc1, reg11, reg5, reg13, reg3, reg11, reg5);
52 loc1 = reg15 + reg3;
53 reg3 = reg15 - reg3;
85 DOTP_CONST_PAIR(reg3, reg1
110 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; local
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/external/vixl/src/aarch32/
H A Dmacro-assembler-aarch32.cc449 CPURegister reg3,
459 PushRegister(reg3);
466 uint32_t args = (reg4.GetType() << 12) | (reg3.GetType() << 8) |
471 int size = reg4.GetRegSizeInBytes() + reg3.GetRegSizeInBytes() +
492 if (reg3.GetType() == CPURegister::kRRegister) {
493 available_registers.Remove(Register(reg3.GetCode()));
507 PushRegister(reg3);
518 PreparePrintfArgument(reg3, &core_count, &vfp_count, &printf_type);
446 Printf(const char* format, CPURegister reg1, CPURegister reg2, CPURegister reg3, CPURegister reg4) argument
/external/v8/src/arm/
H A Dmacro-assembler-arm.cc3711 Register reg3,
3718 if (reg3.is_valid()) regs |= reg3.bit();
3737 Register reg3,
3744 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() +
3750 if (reg3.is_valid()) regs |= reg3.bit();
3709 GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6) argument
3735 AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6, Register reg7, Register reg8) argument
/external/v8/src/full-codegen/arm64/
H A Dfull-codegen-arm64.cc2697 Register reg3) {
2699 __ Push(reg1, reg2, reg3);
2696 PushOperands(Register reg1, Register reg2, Register reg3) argument
/external/v8/src/full-codegen/mips/
H A Dfull-codegen-mips.cc1528 Register reg3) {
1530 __ Push(reg1, reg2, reg3);
1534 Register reg3, Register reg4) {
1536 __ Push(reg1, reg2, reg3, reg4);
1527 PushOperands(Register reg1, Register reg2, Register reg3) argument
1533 PushOperands(Register reg1, Register reg2, Register reg3, Register reg4) argument
/external/v8/src/full-codegen/mips64/
H A Dfull-codegen-mips64.cc1530 Register reg3) {
1532 __ Push(reg1, reg2, reg3);
1536 Register reg3, Register reg4) {
1538 __ Push(reg1, reg2, reg3, reg4);
1529 PushOperands(Register reg1, Register reg2, Register reg3) argument
1535 PushOperands(Register reg1, Register reg2, Register reg3, Register reg4) argument
/external/v8/src/full-codegen/ppc/
H A Dfull-codegen-ppc.cc1492 Register reg3) {
1494 __ Push(reg1, reg2, reg3);
1498 Register reg3, Register reg4) {
1500 __ Push(reg1, reg2, reg3, reg4);
1491 PushOperands(Register reg1, Register reg2, Register reg3) argument
1497 PushOperands(Register reg1, Register reg2, Register reg3, Register reg4) argument
/external/v8/src/full-codegen/s390/
H A Dfull-codegen-s390.cc1454 Register reg3) {
1456 __ Push(reg1, reg2, reg3);
1460 Register reg3, Register reg4) {
1462 __ Push(reg1, reg2, reg3, reg4);
1453 PushOperands(Register reg1, Register reg2, Register reg3) argument
1459 PushOperands(Register reg1, Register reg2, Register reg3, Register reg4) argument
/external/vixl/src/aarch64/
H A Dmacro-assembler-aarch64.cc2788 const Register& reg3,
2792 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit();
2802 const FPRegister& reg3,
2805 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit();
2822 const Register& reg3,
2825 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit();
2832 const FPRegister& reg3,
2835 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit();
2842 const CPURegister& reg3,
2847 const CPURegister regs[] = {reg1, reg2, reg3, reg
2786 Include(const Register& reg1, const Register& reg2, const Register& reg3, const Register& reg4) argument
2800 Include(const FPRegister& reg1, const FPRegister& reg2, const FPRegister& reg3, const FPRegister& reg4) argument
2820 Exclude(const Register& reg1, const Register& reg2, const Register& reg3, const Register& reg4) argument
2830 Exclude(const FPRegister& reg1, const FPRegister& reg2, const FPRegister& reg3, const FPRegister& reg4) argument
2840 Exclude(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4) argument
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/external/v8/src/arm64/
H A Dassembler-arm64.cc213 Register reg3, Register reg4) {
214 CPURegList regs(reg1, reg2, reg3, reg4);
228 const CPURegister& reg3, const CPURegister& reg4,
237 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
265 const CPURegister& reg3, const CPURegister& reg4,
271 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1);
212 GetAllocatableRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, Register reg4) argument
227 AreAliased(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) argument
264 AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) argument
/external/v8/src/ia32/
H A Dmacro-assembler-ia32.cc2647 Register reg3,
2654 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() +
2660 if (reg3.is_valid()) regs |= reg3.bit();
2645 AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6, Register reg7, Register reg8) argument
/external/v8/src/mips64/
H A Dmacro-assembler-mips64.cc6783 Register reg3,
6790 if (reg3.is_valid()) regs |= reg3.bit();
6806 bool AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, argument
6809 int n_of_valid_regs = reg1.is_valid() + reg2.is_valid() + reg3.is_valid() +
6817 if (reg3.is_valid()) regs |= reg3.bit();
6781 GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6) argument
/external/v8/src/x87/
H A Dmacro-assembler-x87.cc2493 Register reg3,
2500 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() +
2506 if (reg3.is_valid()) regs |= reg3.bit();
2491 AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6, Register reg7, Register reg8) argument
/external/v8/src/mips/
H A Dmacro-assembler-mips.cc6376 Register reg3,
6383 if (reg3.is_valid()) regs |= reg3.bit();
6399 bool AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, argument
6402 int n_of_valid_regs = reg1.is_valid() + reg2.is_valid() + reg3.is_valid() +
6410 if (reg3.is_valid()) regs |= reg3.bit();
6374 GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6) argument
/external/v8/src/ppc/
H A Dmacro-assembler-ppc.cc4237 Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, argument
4243 if (reg3.is_valid()) regs |= reg3.bit();
4260 bool AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, argument
4263 int n_of_valid_regs = reg1.is_valid() + reg2.is_valid() + reg3.is_valid() +
4271 if (reg3.is_valid()) regs |= reg3.bit();
/external/v8/src/s390/
H A Dmacro-assembler-s390.cc3183 Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, argument
3189 if (reg3.is_valid()) regs |= reg3.bit();
5259 bool AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, argument
5262 int n_of_valid_regs = reg1.is_valid() + reg2.is_valid() + reg3.is_valid() +
5270 if (reg3.is_valid()) regs |= reg3.bit();
/external/v8/src/x64/
H A Dmacro-assembler-x64.cc5056 Register reg3,
5063 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() +
5069 if (reg3.is_valid()) regs |= reg3.bit();
5054 AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6, Register reg7, Register reg8) argument
/external/sqlite/dist/orig/
H A Dsqlite3.c102593 int reg1, reg2, reg3; local
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/external/sqlite/dist/
H A Dsqlite3.c102593 int reg1, reg2, reg3; local
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