Searched defs:reg_count (Results 1 - 9 of 9) sorted by relevance
/external/mesa3d/src/gallium/drivers/ilo/ |
H A D | ilo_render.c | 265 int reg_count = 0, i; local 282 reg_count = 1; 286 reg_count = 1; 290 reg_count = ARRAY_SIZE(pipeline_statistics_regs); 297 assert(!reg_count); 306 } else if (reg_count) { 310 for (i = 0; i < reg_count; i++) {
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/external/v8/src/compiler/ |
H A D | bytecode-analysis.cc | 163 uint32_t reg_count = accessor.GetRegisterCountOperand(i); local 165 for (uint32_t j = 0; j < reg_count; ++j) {
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/external/vixl/test/aarch64/ |
H A D | test-utils-aarch64.cc | 277 int reg_count, 281 for (unsigned n = 0; (n < kNumberOfRegisters) && (i < reg_count); n++) { 298 VIXL_ASSERT(CountSetBits(list, kNumberOfRegisters) == reg_count); 308 int reg_count, 312 for (unsigned n = 0; (n < kNumberOfFPRegisters) && (i < reg_count); n++) { 329 VIXL_ASSERT(CountSetBits(list, kNumberOfFPRegisters) == reg_count); 273 PopulateRegisterArray(Register* w, Register* x, Register* r, int reg_size, int reg_count, RegList allowed) argument 304 PopulateFPRegisterArray(FPRegister* s, FPRegister* d, FPRegister* v, int reg_size, int reg_count, RegList allowed) argument
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H A D | test-assembler-aarch64.cc | 14038 // supports (where a reg_count argument would otherwise be provided). 14043 // * Push <reg_count> registers with size <reg_size>. 14045 // * Pop <reg_count> registers to restore the original contents. 14050 static void PushPopSimpleHelper(int reg_count, argument 14062 if (reg_count == kPushPopUseMaxRegCount) { 14063 reg_count = CountSetBits(allowed, kNumberOfRegisters); 14069 PopulateRegisterArray(NULL, x, r, reg_size, reg_count, allowed); 14090 for (i = 0; i < reg_count; i++) { 14102 for (i = reg_count; i >= 4; i -= 4) { 14132 for (i = 0; i <= (reg_count 14293 PushPopFPSimpleHelper(int reg_count, int claim, int reg_size, PushPopMethod push_method, PushPopMethod pop_method) argument 14638 PushPopWXOverlapHelper(int reg_count, int claim) argument [all...] |
/external/mesa3d/src/gallium/drivers/radeonsi/ |
H A D | si_perfcounter.c | 534 unsigned reg_count = count + MIN2(count, regs->num_multi); local 535 reg_count += regs->num_prelude; 538 radeon_set_uconfig_reg_seq(cs, reg_base, reg_count); 548 reg_base -= (reg_count - 1) * 4; 549 radeon_set_uconfig_reg_seq(cs, reg_base, reg_count);
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_fs.cpp | 1673 int reg_count = 0; local 1676 vgrf_to_reg[i] = reg_count; 1677 reg_count += alloc.sizes[i]; 1686 bool split_points[reg_count]; 1721 int new_virtual_grf[reg_count]; 1722 int new_reg_offset[reg_count]; 1757 assert(reg == reg_count); 4505 unsigned reg_count = DIV_ROUND_UP(inst->size_written, REG_SIZE); 4508 reg_count = MAX2(reg_count, DIV_ROUND_U [all...] |
H A D | brw_context.h | 1596 brw_register_blocks(int reg_count) argument 1598 return ALIGN(reg_count, 16) / 16 - 1;
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/external/mesa3d/src/amd/vulkan/ |
H A D | radv_cmd_buffer.c | 745 unsigned reg_offset = 0, reg_count = 0; local 751 ++reg_count; 757 ++reg_count; 761 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0)); 772 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
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/external/google-breakpad/src/third_party/libdisasm/ |
H A D | libdis.h | 127 reg_count = 0x40000 /* array/rep/loop counter */ enumerator in enum:x86_reg_type
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