/art/compiler/debug/dwarf/ |
H A D | expression.h | 69 void WriteOpFbreg(int32_t stack_offset) { argument 71 PushSleb128(stack_offset);
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/art/compiler/utils/arm/ |
H A D | assembler_arm_vixl.cc | 387 void ArmVIXLAssembler::StoreRegisterList(RegList regs, size_t stack_offset) { argument 393 if (stack_offset != 0) { 396 ___ Add(base, sp, Operand::From(stack_offset)); 401 ___ Str(vixl32::Register(i), MemOperand(sp, stack_offset)); 402 stack_offset += kRegSizeInBytes; 408 void ArmVIXLAssembler::LoadRegisterList(RegList regs, size_t stack_offset) { argument 414 if (stack_offset != 0) { 416 ___ Add(base, sp, Operand::From(stack_offset)); 421 ___ Ldr(vixl32::Register(i), MemOperand(sp, stack_offset)); 422 stack_offset [all...] |
/art/compiler/optimizing/ |
H A D | code_generator.cc | 1520 size_t stack_offset = codegen->GetFirstRegisterSlotInSlowPath(); local 1526 locations->SetStackBit(stack_offset / kVRegSize); 1528 DCHECK_LT(stack_offset, codegen->GetFrameSize() - codegen->FrameEntrySpillSize()); 1530 saved_core_stack_offsets_[i] = stack_offset; 1531 stack_offset += codegen->SaveCoreRegister(stack_offset, i); 1536 DCHECK_LT(stack_offset, codegen->GetFrameSize() - codegen->FrameEntrySpillSize()); 1538 saved_fpu_stack_offsets_[i] = stack_offset; 1539 stack_offset += codegen->SaveFloatingPointRegister(stack_offset, 1544 size_t stack_offset = codegen->GetFirstRegisterSlotInSlowPath(); local [all...] |
H A D | code_generator_mips64.cc | 99 size_t stack_offset = calling_convention.GetStackOffsetOf(stack_index_); local 100 next_location = DataType::Is64BitType(type) ? Location::DoubleStackSlot(stack_offset) 101 : Location::StackSlot(stack_offset); 1050 int stack_offset = ensure_scratch.IsSpilled() ? kMips64DoublewordSize : 0; local 1054 index1 + stack_offset); 1058 index2 + stack_offset); 1062 index2 + stack_offset); 1063 __ StoreToOffset(store_type, TMP, SP, index1 + stack_offset);
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H A D | code_generator_arm64.cc | 220 size_t stack_offset = codegen->GetFirstRegisterSlotInSlowPath(); local 225 locations->SetStackBit(stack_offset / kVRegSize); 227 DCHECK_LT(stack_offset, codegen->GetFrameSize() - codegen->FrameEntrySpillSize()); 229 saved_core_stack_offsets_[i] = stack_offset; 230 stack_offset += kXRegSizeInBytes; 235 DCHECK_LT(stack_offset, codegen->GetFrameSize() - codegen->FrameEntrySpillSize()); 237 saved_fpu_stack_offsets_[i] = stack_offset; 238 stack_offset += kDRegSizeInBytes; 1361 size_t stack_offset = calling_convention.GetStackOffsetOf(stack_index_); local 1362 next_location = DataType::Is64BitType(type) ? Location::DoubleStackSlot(stack_offset) [all...] |
H A D | code_generator_arm_vixl.cc | 191 size_t stack_offset) { 196 __ Vstr(vixl32::SRegister(first), MemOperand(sp, stack_offset)); 197 return stack_offset + kSRegSizeInBytes; 200 __ Vstr(vixl32::SRegister(first++), MemOperand(sp, stack_offset)); 201 stack_offset += kSRegSizeInBytes; 216 __ Vstr(d_reg, MemOperand(sp, stack_offset)); 220 if (stack_offset != 0) { 222 __ Add(base, sp, Operand::From(stack_offset)); 226 stack_offset += number_of_d_regs * kDRegSizeInBytes; 230 __ Vstr(vixl32::SRegister(last + 1), MemOperand(sp, stack_offset)); 188 SaveContiguousSRegisterList(size_t first, size_t last, CodeGenerator* codegen, size_t stack_offset) argument 237 RestoreContiguousSRegisterList(size_t first, size_t last, CodeGenerator* codegen, size_t stack_offset) argument 338 size_t stack_offset = codegen->GetFirstRegisterSlotInSlowPath(); local 376 size_t stack_offset = codegen->GetFirstRegisterSlotInSlowPath(); local 6933 int stack_offset = ensure_scratch.IsSpilled() ? kArmWordSize : 0; local 8873 int stack_offset = slow_path->GetStackOffsetOfCoreRegister(RegisterFrom(location).GetCode()); local [all...] |
H A D | code_generator_mips.cc | 102 size_t stack_offset = calling_convention.GetStackOffsetOf(stack_index_); local 103 next_location = Location::StackSlot(stack_offset); 122 size_t stack_offset = calling_convention.GetStackOffsetOf(stack_index_); local 123 next_location = Location::DoubleStackSlot(stack_offset); 138 size_t stack_offset = calling_convention.GetStackOffsetOf(stack_index_); local 139 next_location = DataType::Is64BitType(type) ? Location::DoubleStackSlot(stack_offset) 140 : Location::StackSlot(stack_offset); 1229 int stack_offset = ensure_scratch.IsSpilled() ? kStackAlignment : 0; local 1230 for (int i = 0; i <= (double_slot ? 1 : 0); i++, stack_offset += kMipsWordSize) { 1234 index1 + stack_offset); 7786 int stack_offset = slow_path->GetStackOffsetOfCoreRegister(location.AsRegister<Register>()); local [all...] |
H A D | code_generator_x86.cc | 4505 int stack_offset = slow_path->GetStackOffsetOfCoreRegister(location.AsRegister<Register>()); local 4506 __ movl(temp, Address(ESP, stack_offset)); 5770 int stack_offset = ensure_scratch.IsSpilled() ? kX86WordSize : 0; local 5774 __ movl(temp_reg, Address(ESP, src + stack_offset)); 5775 __ movl(Address(ESP, dst + stack_offset), temp_reg); 5776 stack_offset += kX86WordSize; 5930 int stack_offset = ensure_scratch.IsSpilled() ? kX86WordSize : 0; local 5931 __ movl(static_cast<Register>(ensure_scratch.GetRegister()), Address(ESP, mem + stack_offset)); 5932 __ movl(Address(ESP, mem + stack_offset), reg); 5941 int stack_offset local 5964 int stack_offset = ensure_scratch1.IsSpilled() ? kX86WordSize : 0; local [all...] |
H A D | code_generator_x86_64.cc | 5370 int stack_offset = ensure_scratch.IsSpilled() ? kX86_64WordSize : 0; local 5371 __ movl(CpuRegister(TMP), Address(CpuRegister(RSP), mem1 + stack_offset)); local 5373 Address(CpuRegister(RSP), mem2 + stack_offset)); local 5374 __ movl(Address(CpuRegister(RSP), mem2 + stack_offset), CpuRegister(TMP)); local 5375 __ movl(Address(CpuRegister(RSP), mem1 + stack_offset), local 5383 int stack_offset = ensure_scratch.IsSpilled() ? kX86_64WordSize : 0; local 5388 Address(CpuRegister(RSP), mem1 + stack_offset)); local 5390 Address(CpuRegister(RSP), mem2 + stack_offset)); local 5391 __ movq(Address(CpuRegister(RSP), mem2 + stack_offset), local 5393 __ movq(Address(CpuRegister(RSP), mem1 + stack_offset), local [all...] |
/art/runtime/ |
H A D | thread.cc | 3701 const size_t stack_offset = stack_index * kFrameSlotSize; local 3702 FindWithType(stack_offset,
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/art/compiler/utils/mips/ |
H A D | assembler_mips.cc | 4769 int stack_offset = frame_size - kFramePointerSize; local 4770 StoreToOffset(kStoreWord, RA, SP, stack_offset); 4771 cfi_.RelOffset(DWARFReg(RA), stack_offset); local 4773 stack_offset -= kFramePointerSize; 4775 StoreToOffset(kStoreWord, reg, SP, stack_offset); 4776 cfi_.RelOffset(DWARFReg(reg), stack_offset); local 4810 int stack_offset = frame_size - (callee_save_regs.size() * kFramePointerSize) - kFramePointerSize; local 4813 LoadFromOffset(kLoadWord, reg, SP, stack_offset); 4815 stack_offset += kFramePointerSize; 4817 LoadFromOffset(kLoadWord, RA, SP, stack_offset); [all...] |
/art/compiler/utils/mips64/ |
H A D | assembler_mips64.cc | 3601 int stack_offset = frame_size - kFramePointerSize; local 3602 StoreToOffset(kStoreDoubleword, RA, SP, stack_offset); 3603 cfi_.RelOffset(DWARFReg(RA), stack_offset); local 3605 stack_offset -= kFramePointerSize; 3607 StoreToOffset(kStoreDoubleword, reg, SP, stack_offset); 3608 cfi_.RelOffset(DWARFReg(reg), stack_offset); local 3643 int stack_offset = frame_size - (callee_save_regs.size() * kFramePointerSize) - kFramePointerSize; local 3646 LoadFromOffset(kLoadDoubleword, reg, SP, stack_offset); 3648 stack_offset += kFramePointerSize; 3650 LoadFromOffset(kLoadDoubleword, RA, SP, stack_offset); [all...] |