/external/tensorflow/tensorflow/compiler/tf2xla/ |
H A D | test_util.cc | 32 InstantiationResult inst; local 34 InstantiateFunction(*fdef, AttrSlice(), get_func_sig, &inst)); 35 result->arg_types = inst.arg_types; 36 result->ret_types = inst.ret_types; 37 for (NodeDef& n : inst.nodes) {
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_fs_saturate_propagation.cpp | 51 foreach_inst_in_block_reverse(fs_inst, inst, block) { 54 if (inst->opcode != BRW_OPCODE_MOV || 55 !inst->saturate || 56 inst->dst.file != VGRF || 57 inst->dst.type != inst->src[0].type || 58 inst->src[0].file != VGRF || 59 inst->src[0].abs) 62 int src_var = v->live_intervals->var_from_reg(inst->src[0]); 66 foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) { [all...] |
H A D | brw_fs.cpp | 48 const fs_inst *inst); 192 fs_inst *inst = bld.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL, local 194 inst->size_written = 4 * vec4_result.component_size(inst->exec_size); 223 fs_inst::equals(fs_inst *inst) const 225 return (opcode == inst->opcode && 226 dst.equals(inst->dst) && 227 src[0].equals(inst->src[0]) && 228 src[1].equals(inst->src[1]) && 229 src[2].equals(inst 854 flag_mask(const fs_inst *inst) argument 905 implied_mrf_writes(fs_inst *inst) argument 1345 fs_inst *inst; local 1542 convert_attr_sources_to_hw_regs(fs_inst *inst) argument [all...] |
H A D | brw_eu_validate.c | 58 src0_is_null(const struct gen_device_info *devinfo, const brw_inst *inst) argument 60 return brw_inst_src0_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE && 61 brw_inst_src0_da_reg_nr(devinfo, inst) == BRW_ARF_NULL; 65 src1_is_null(const struct gen_device_info *devinfo, const brw_inst *inst) argument 67 return brw_inst_src1_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE && 68 brw_inst_src1_da_reg_nr(devinfo, inst) == BRW_ARF_NULL; 72 src0_is_grf(const struct gen_device_info *devinfo, const brw_inst *inst) argument 74 return brw_inst_src0_reg_file(devinfo, inst) == BRW_GENERAL_REGISTER_FILE; 79 const brw_inst *inst) 82 brw_opcode_desc(devinfo, brw_inst_opcode(devinfo, inst)); 78 num_sources_from_inst(const struct gen_device_info *devinfo, const brw_inst *inst) argument 127 is_unsupported_inst(const struct gen_device_info *devinfo, const brw_inst *inst) argument 144 const brw_inst *inst = store + src_offset; local [all...] |
H A D | brw_vec4.cpp | 312 vec4_visitor::implied_mrf_writes(vec4_instruction *inst) argument 314 if (inst->mlen == 0 || inst->is_send_from_grf()) 317 switch (inst->opcode) { 361 return inst->header_size; 389 foreach_inst_in_block_safe(vec4_instruction, inst, block) { 398 if (inst->opcode == BRW_OPCODE_MOV && 399 inst->src[0].file == IMM && 400 inst->predicate == BRW_PREDICATE_NONE && 401 inst 913 is_dep_ctrl_unsafe(const vec4_instruction *inst) argument 1477 vec4_instruction *inst = (vec4_instruction *)be_inst; local 1934 vec4_instruction *inst = local 2069 get_lowered_simd_width(const struct gen_device_info *devinfo, enum shader_dispatch_mode dispatch_mode, unsigned stage, const vec4_instruction *inst) argument 2121 dst_src_regions_overlap(vec4_instruction *inst) argument 2242 is_align1_df(vec4_instruction *inst) argument 2281 is_gen7_supported_64bit_swizzle(vec4_instruction *inst, unsigned arg) argument 2311 is_supported_64bit_region(vec4_instruction *inst, unsigned arg) argument 2470 apply_logical_swizzle(struct brw_reg *hw_reg, vec4_instruction *inst, int arg) argument [all...] |
H A D | brw_fs_generator.cpp | 57 brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen, bool compressed) argument 84 const unsigned phys_width = compressed ? inst->exec_size / 2 : 85 inst->exec_size; 194 fs_generator::fire_fb_write(fs_inst *inst, argument 213 if (inst->opcode == FS_OPCODE_REP_FB_WRITE) 216 if (!inst->group) 220 } else if (inst->exec_size == 16) 226 prog_data->binding_table.render_target_start + inst->target; 228 bool last_render_target = inst->eot || 239 inst 247 generate_fb_write(fs_inst *inst, struct brw_reg payload) argument 356 generate_fb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload) argument 372 generate_mov_indirect(fs_inst *inst, struct brw_reg dst, struct brw_reg reg, struct brw_reg indirect_byte_offset) argument 449 generate_urb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg header) argument 475 generate_urb_write(fs_inst *inst, struct brw_reg payload) argument 504 generate_cs_terminate(fs_inst *inst, struct brw_reg payload) argument 535 generate_barrier(fs_inst *inst, struct brw_reg src) argument 542 generate_linterp(fs_inst *inst, struct brw_reg dst, struct brw_reg *src) argument 579 generate_get_buffer_size(fs_inst *inst, struct brw_reg dst, struct brw_reg src, struct brw_reg surf_index) argument 623 generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src, struct brw_reg surface_index, struct brw_reg sampler_index) argument 1067 generate_discard_jump(fs_inst *inst) argument 1080 generate_scratch_write(fs_inst *inst, struct brw_reg src) argument 1111 generate_scratch_read(fs_inst *inst, struct brw_reg dst) argument 1121 generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst) argument 1129 generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst, struct brw_reg index, struct brw_reg offset) argument 1150 generate_uniform_pull_constant_load_gen7(fs_inst *inst, struct brw_reg dst, struct brw_reg index, struct brw_reg payload) argument 1208 generate_varying_pull_constant_load_gen4(fs_inst *inst, struct brw_reg dst, struct brw_reg index) argument 1269 generate_varying_pull_constant_load_gen7(fs_inst *inst, struct brw_reg dst, struct brw_reg index, struct brw_reg offset) argument 1350 generate_mov_dispatch_to_flags(fs_inst *inst) argument 1367 generate_pixel_interpolator_query(fs_inst *inst, struct brw_reg dst, struct brw_reg src, struct brw_reg msg_data, unsigned msg_type) argument 1390 generate_set_sample_id(fs_inst *inst, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1) argument 1415 generate_pack_half_2x16_split(fs_inst *inst, struct brw_reg dst, struct brw_reg x, struct brw_reg y) argument 1454 generate_unpack_half_2x16_split(fs_inst *inst, struct brw_reg dst, struct brw_reg src) argument 1483 generate_shader_time_add(fs_inst *inst, struct brw_reg payload, struct brw_reg offset, struct brw_reg value) argument [all...] |
/external/webrtc/webrtc/modules/audio_processing/ns/ |
H A D | nsx_core_mips.c | 26 void WebRtcNsx_SpeechNoiseProb(NoiseSuppressionFixedC* inst, argument 49 for (i = 0; i < inst->magnLen; i++) { 52 r2 = inst->logLrtTimeAvgW32[i]; 105 inst->logLrtTimeAvgW32[i] = r2; 109 inst->featureLogLrt = (logLrtTimeAvgKsumFX * BIN_SIZE_LRT) >> 110 (inst->stages + 11); 123 tmp32no1 = logLrtTimeAvgKsumFX - inst->thresholdLogLrt; // Q12 124 nShifts = 7 - inst->stages; // WIDTH_PR_MAP_SHIFT - inst->stages + 5; 146 indPriorFX = inst 331 WebRtcNsx_AnalysisUpdate_mips(NoiseSuppressionFixedC* inst, int16_t* out, int16_t* new_speech) argument 505 WebRtcNsx_SynthesisUpdate_mips(NoiseSuppressionFixedC* inst, int16_t* out_frame, int16_t gain_factor) argument 755 WebRtcNsx_PrepareSpectrum_mips(NoiseSuppressionFixedC* inst, int16_t* freq_buf) argument 861 WebRtcNsx_Denormalize_mips(NoiseSuppressionFixedC* inst, int16_t* in, int factor) argument 951 WebRtcNsx_NormalizeRealBuffer_mips(NoiseSuppressionFixedC* inst, const int16_t* in, int16_t* out) argument [all...] |
H A D | nsx_core_c.c | 26 void WebRtcNsx_SpeechNoiseProb(NoiseSuppressionFixedC* inst, argument 42 for (i = 0; i < inst->magnLen; i++) { 57 // inst->logLrtTimeAvg[i] += LRT_TAVG * (besselTmp - log(snrLocPrior) 58 // - inst->logLrtTimeAvg[i]); 68 // tmp32no1 = LRT_TAVG * (log(snrLocPrior) + inst->logLrtTimeAvg[i]) in Q12. 69 tmp32no1 = (logTmp + inst->logLrtTimeAvgW32[i]) / 2; 70 inst->logLrtTimeAvgW32[i] += (besselTmpFX32 - tmp32no1); // Q12 72 logLrtTimeAvgKsumFX += inst->logLrtTimeAvgW32[i]; // Q12 74 inst->featureLogLrt = (logLrtTimeAvgKsumFX * BIN_SIZE_LRT) >> 75 (inst [all...] |
H A D | nsx_core_neon.c | 59 static void UpdateNoiseEstimateNeon(NoiseSuppressionFixedC* inst, int offset) { argument 68 int16_t tmp16 = WebRtcSpl_MaxValueW16(inst->noiseEstLogQuantile + offset, 69 inst->magnLen); 72 inst->qNoise = 14 - (int) WEBRTC_SPL_MUL_16_16_RSFT_WITH_ROUND(kExp2Const, 76 int32x4_t qNoise32x4 = vdupq_n_s32(inst->qNoise); 78 for (ptr_noiseEstLogQuantile = &inst->noiseEstLogQuantile[offset], 79 ptr_noiseEstQuantile = &inst->noiseEstQuantile[0]; 80 ptr_noiseEstQuantile < &inst->noiseEstQuantile[inst->magnLen - 3]; 83 // tmp32no2 = kExp2Const * inst 134 WebRtcNsx_NoiseEstimationNeon(NoiseSuppressionFixedC* inst, uint16_t* magn, uint32_t* noise, int16_t* q_noise) argument 355 WebRtcNsx_PrepareSpectrumNeon(NoiseSuppressionFixedC* inst, int16_t* freq_buf) argument 445 WebRtcNsx_SynthesisUpdateNeon(NoiseSuppressionFixedC* inst, int16_t* out_frame, int16_t gain_factor) argument 537 WebRtcNsx_AnalysisUpdateNeon(NoiseSuppressionFixedC* inst, int16_t* out, int16_t* new_speech) argument [all...] |
/external/mesa3d/src/gallium/drivers/r300/compiler/ |
H A D | r500_fragprog_emit.c | 159 static unsigned int translate_arg_rgb(struct rc_pair_instruction *inst, int arg) argument 161 unsigned int t = inst->RGB.Arg[arg].Source; 163 t |= inst->RGB.Arg[arg].Negate << 11; 164 t |= inst->RGB.Arg[arg].Abs << 12; 167 t |= fix_hw_swizzle(GET_SWZ(inst->RGB.Arg[arg].Swizzle, comp)) << (3*comp + 2); 172 static unsigned int translate_arg_alpha(struct rc_pair_instruction *inst, int i) argument 174 unsigned int t = inst->Alpha.Arg[i].Source; 175 t |= fix_hw_swizzle(GET_SWZ(inst->Alpha.Arg[i].Swizzle, 0)) << 2; 176 t |= inst->Alpha.Arg[i].Negate << 5; 177 t |= inst 235 emit_paired(struct r300_fragment_program_compiler *c, struct rc_pair_instruction *inst) argument 371 emit_tex(struct r300_fragment_program_compiler *c, struct rc_sub_instruction *inst) argument 443 emit_flowcontrol(struct emit_state * s, struct rc_instruction * inst) argument [all...] |
H A D | radeon_vert_fc.c | 61 static void mark_write(void * userdata, struct rc_instruction * inst, argument 79 struct rc_instruction * inst; local 81 for(inst = fc_state->C->Program.Instructions.Next; 82 inst != &fc_state->C->Program.Instructions; 83 inst = inst->Next) { 84 rc_for_all_writes_mask(inst, mark_write, writemasks); 108 struct rc_instruction * inst, 112 rc_insert_new_instruction(fc_state->C, inst->Prev); 159 struct rc_instruction * inst, 107 lower_bgnloop( struct rc_instruction * inst, struct vert_fc_state * fc_state) argument 158 lower_brk( struct rc_instruction * inst, struct vert_fc_state * fc_state) argument 176 lower_endloop( struct rc_instruction * inst, struct vert_fc_state * fc_state) argument 190 lower_if( struct rc_instruction * inst, struct vert_fc_state * fc_state) argument 234 struct rc_instruction * inst; local [all...] |
H A D | radeon_program_print.c | 198 struct rc_presub_instruction inst) 201 switch(inst.Opcode){ 204 rc_print_register(f, inst.SrcReg[0].File, 205 inst.SrcReg[0].Index,inst.SrcReg[0].RelAddr); 208 rc_print_register(f, inst.SrcReg[1].File, 209 inst.SrcReg[1].Index,inst.SrcReg[1].RelAddr); 211 rc_print_register(f, inst.SrcReg[0].File, 212 inst 197 rc_print_presub_instruction(FILE * f, struct rc_presub_instruction inst) argument 232 rc_print_src_register(FILE * f, struct rc_instruction * inst, struct rc_src_register src) argument 280 rc_print_normal_instruction(FILE * f, struct rc_instruction * inst, unsigned *branch_depth) argument 343 struct rc_pair_instruction * inst = &fullinst->U.P; local 470 struct rc_instruction *inst; local [all...] |
H A D | radeon_dataflow.h | 48 typedef void (*rc_read_write_chan_fn)(void * userdata, struct rc_instruction * inst, 50 void rc_for_all_reads_chan(struct rc_instruction * inst, rc_read_write_chan_fn cb, void * userdata); 51 void rc_for_all_writes_chan(struct rc_instruction * inst, rc_read_write_chan_fn cb, void * userdata); 53 typedef void (*rc_read_write_mask_fn)(void * userdata, struct rc_instruction * inst, 55 void rc_for_all_reads_mask(struct rc_instruction * inst, rc_read_write_mask_fn cb, void * userdata); 56 void rc_for_all_writes_mask(struct rc_instruction * inst, rc_read_write_mask_fn cb, void * userdata); 58 typedef void (*rc_read_src_fn)(void * userdata, struct rc_instruction * inst, 60 void rc_for_all_reads_src(struct rc_instruction * inst, rc_read_src_fn cb, 64 struct rc_instruction * inst, struct rc_pair_instruction_arg * arg, 66 void rc_pair_for_all_reads_arg(struct rc_instruction * inst, [all...] |
H A D | r300_fragprog_emit.c | 151 static int emit_alu(struct r300_emit_state * emit, struct rc_pair_instruction* inst) argument 164 code->alu.inst[ip].rgb_inst = translate_rgb_opcode(c, inst->RGB.Opcode); 165 code->alu.inst[ip].alpha_inst = translate_alpha_opcode(c, inst->Alpha.Opcode); 169 unsigned int src = use_source(code, inst->RGB.Src[j]); 171 if (inst->RGB.Src[j].Index >= R300_PFS_NUM_TEMP_REGS) 172 code->alu.inst[ip].r400_ext_addr |= R400_ADDR_EXT_RGB_MSB_BIT(j); 174 code->alu.inst[ip].rgb_addr |= src << (6*j); 177 src = use_source(code, inst 318 struct rc_pair_instruction inst; local 423 emit_tex(struct r300_emit_state * emit, struct rc_instruction * inst) argument [all...] |
/external/mesa3d/src/gallium/drivers/vc4/ |
H A D | vc4_qpu_disasm.c | 296 print_alu_dst(uint64_t inst, bool is_mul) argument 298 bool is_a = is_mul == ((inst & QPU_WS) != 0); 300 QPU_GET_FIELD(inst, QPU_WADDR_MUL) : 301 QPU_GET_FIELD(inst, QPU_WADDR_ADD)); 303 uint32_t pack = QPU_GET_FIELD(inst, QPU_PACK); 312 if (is_mul && (inst & QPU_PM)) { 314 } else if (is_a && !(inst & QPU_PM)) { 320 print_alu_src(uint64_t inst, uint32_t mux, bool is_mul) argument 325 QPU_GET_FIELD(inst, QPU_RADDR_A) : 326 QPU_GET_FIELD(inst, QPU_RADDR_ 362 print_add_op(uint64_t inst) argument 395 print_mul_op(uint64_t inst) argument 428 print_load_imm(uint64_t inst) argument 455 uint64_t inst = instructions[i]; local [all...] |
H A D | vc4_qir_lower_uniforms.c | 75 is_lowerable_uniform(struct qinst *inst, int i) argument 77 if (inst->src[i].file != QFILE_UNIF) 79 if (qir_is_tex(inst)) 80 return i != qir_get_tex_uniform_src(inst); 88 qir_get_instruction_uniform_count(struct qinst *inst) argument 92 for (int i = 0; i < qir_get_nsrc(inst); i++) { 93 if (inst->src[i].file != QFILE_UNIF) 98 if (inst->src[j].file == QFILE_UNIF && 99 inst->src[j].index == inst [all...] |
/external/pcre/dist2/src/sljit/ |
H A D | sljitNativeX86_64.c | 31 sljit_u8 *inst; local 33 inst = (sljit_u8*)ensure_buf(compiler, 1 + 2 + sizeof(sljit_sw)); 34 FAIL_IF(!inst); 36 *inst++ = REX_W | ((reg_map[reg] <= 7) ? 0 : REX_B); 37 *inst++ = MOV_r_i32 + (reg_map[reg] & 0x7); 38 sljit_unaligned_store_sw(inst, imm); 95 sljit_u8 *inst; local 109 inst = (sljit_u8*)ensure_buf(compiler, 1 + size); 110 FAIL_IF(!inst); 113 *inst 259 sljit_u8 *inst; local 333 sljit_u8 *inst; local 352 sljit_u8 *inst; local 558 sljit_u8 *inst; local 594 sljit_u8 *inst; local 631 sljit_u8 *inst; local 696 sljit_u8* inst; local [all...] |
H A D | sljitNativeX86_32.c | 31 sljit_u8 *inst; local 33 inst = (sljit_u8*)ensure_buf(compiler, 1 + 1 + sizeof(sljit_sw)); 34 FAIL_IF(!inst); 36 *inst++ = opcode; 37 sljit_unaligned_store_sw(inst, imm); 71 sljit_u8 *inst; local 86 inst = (sljit_u8*)ensure_buf(compiler, 1 + size); 87 FAIL_IF(!inst); 93 *inst++ = MOV_r_rm; 94 *inst 211 sljit_u8 *inst; local 280 sljit_u8 *inst; local 443 sljit_u8 *inst; local 481 sljit_u8 *inst; local 512 sljit_u8 *inst; local [all...] |
/external/capstone/ |
H A D | MCInst.h | 78 void MCOperand_CreateReg0(MCInst *inst, unsigned Reg); 81 MCOperand *MCOperand_CreateReg1(MCInst *inst, unsigned Reg); 84 void MCOperand_CreateImm0(MCInst *inst, int64_t Val); 87 MCOperand *MCOperand_CreateImm1(MCInst *inst, int64_t Val); 111 void MCInst_Init(MCInst *inst); 113 void MCInst_clear(MCInst *inst); 116 void MCInst_insert0(MCInst *inst, int index, MCOperand *Op); 118 void MCInst_setOpcode(MCInst *inst, unsigned Op); 122 void MCInst_setOpcodePub(MCInst *inst, unsigned Op); 126 MCOperand *MCInst_getOperand(MCInst *inst, unsigne [all...] |
/external/llvm/test/MC/ARM/ |
H A D | inst-directive.s | 11 .section .inst.arm_inst 17 .inst 0xdefe 20 @ CHECK: Name: .inst.arm_inst 30 .section .inst.thumb_inst_n 36 .inst.n 0xdefe 39 @ CHECK: Name: .inst.thumb_inst_n 49 .section .inst.thumb_inst_w 55 .inst.w 0x00000000 58 @ CHECK: Name: .inst.thumb_inst_w 68 .section .inst [all...] |
/external/vixl/tools/ |
H A D | make_instruction_doc_aarch64.pl | 38 my %inst = (); # Global hash of instructions. 67 $inst{$p}->{'type'} = $type; 68 $inst{$p}->{'mnemonic'} = $i; 69 $inst{$p}->{'description'} = $d; 92 $inst{$a}->{'mnemonic'} cmp $inst{$b}->{'mnemonic'} || 93 $inst{$a}->{'description'} cmp $inst{$b}->{'description'} || 106 foreach my $i (sort inst_sort keys(%inst)) 108 next if($inst{ [all...] |
/external/mesa3d/src/mesa/state_tracker/ |
H A D | st_tgsi_lower_yuv.c | 101 struct tgsi_full_instruction inst; local 103 inst = tgsi_default_full_instruction(); 104 inst.Instruction.Opcode = TGSI_OPCODE_TEX; 105 inst.Instruction.Texture = 1; 106 inst.Texture.Texture = TGSI_TEXTURE_2D; 107 inst.Instruction.NumDstRegs = 1; 108 inst.Instruction.NumSrcRegs = 2; 109 inst.Src[1].Register.File = TGSI_FILE_SAMPLER; 110 inst.Src[1].Register.Index = samp; 112 return inst; 118 struct tgsi_full_instruction inst; local 132 struct tgsi_full_instruction inst; local 250 struct tgsi_full_instruction inst; local 304 struct tgsi_full_instruction inst; local 339 struct tgsi_full_instruction inst; local 384 transform_instr(struct tgsi_transform_context *tctx, struct tgsi_full_instruction *inst) argument [all...] |
H A D | st_cb_bitmap_shader.c | 56 struct tgsi_full_instruction inst; local 105 inst = tgsi_default_full_instruction(); 106 inst.Instruction.Opcode = TGSI_OPCODE_KILL_IF; 107 inst.Instruction.NumDstRegs = 0; 108 inst.Instruction.NumSrcRegs = 1; 110 inst.Src[0].Register.File = TGSI_FILE_TEMPORARY; 111 inst.Src[0].Register.Index = 0; 112 inst.Src[0].Register.Negate = 1; 113 inst.Src[0].Register.SwizzleX = TGSI_SWIZZLE_X; 115 inst [all...] |
/external/mesa3d/src/gallium/drivers/r300/compiler/tests/ |
H A D | rc_test_helpers.h | 40 struct rc_instruction * inst, 45 struct rc_instruction * inst, 49 struct rc_instruction * inst, 55 struct rc_instruction * inst,
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/external/swiftshader/third_party/subzero/crosstest/ |
H A D | test_sync_atomic.h | 17 #define X(inst, type) \ 18 type test_##inst(bool fetch_first, volatile type *ptr, type a); \ 19 type test_alloca_##inst(bool fetch, volatile type *ptr, type a); \ 20 type test_const_##inst(bool fetch, volatile type *ptr, type ignored);
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