Searched refs:opc (Results 26 - 50 of 112) sorted by relevance

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/external/f2fs-tools/tools/sg_write_buffer/include/
H A Dfreebsd_nvme_ioctl.h39 uint16_t opc : 8; /* opcode */ member in struct:nvme_command
103 * * opc (opcode)
/external/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp637 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2, local
641 opc = QII->getInvertedPredicatedOpcode(opc);
645 QII->get(opc))
656 QII->get(opc))
662 QII->get(opc))
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
H A DARMAsmBackend.cpp241 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 local
244 opc = 2; // 0b0010
249 return ARM_AM::getSOImmVal(Value) | (opc << 21);
254 unsigned opc = 0; local
257 opc = 5;
260 uint32_t out = (opc << 21);
/external/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_compiler.c1037 uint8_t opc; member in struct:instr_translater
1052 instr.opcode = t->opc;
1240 .opcode = t->opc,
1740 INSTR(MOV, trans_instr, .opc = INST_OPCODE_MOV, .src = {2, -1, -1}),
1741 INSTR(RCP, trans_instr, .opc = INST_OPCODE_RCP, .src = {2, -1, -1}),
1742 INSTR(RSQ, trans_instr, .opc = INST_OPCODE_RSQ, .src = {2, -1, -1}),
1743 INSTR(MUL, trans_instr, .opc = INST_OPCODE_MUL, .src = {0, 1, -1}),
1744 INSTR(ADD, trans_instr, .opc = INST_OPCODE_ADD, .src = {0, 2, -1}),
1745 INSTR(DP3, trans_instr, .opc = INST_OPCODE_DP3, .src = {0, 1, -1}),
1746 INSTR(DP4, trans_instr, .opc
1843 const unsigned opc = inst->Instruction.Opcode; local
[all...]
/external/mesa3d/src/gallium/drivers/freedreno/ir3/
H A Dir3_group.c72 instr->opc = OPC_MOV;
137 if (instr->opc == OPC_META_PHI)
188 if (instr->opc == OPC_META_FI)
H A Dir3_ra.c347 if (instr->opc == OPC_META_FI) {
441 if (d->opc == OPC_META_PHI) {
461 if (d->opc == OPC_META_FO) {
472 debug_assert(instr->opc == OPC_META_FO);
903 switch (opc_cat(instr->opc)) {
908 switch (instr->opc) {
910 instr->opc = OPC_MAD_F16;
913 instr->opc = OPC_SEL_B16;
916 instr->opc = OPC_SEL_S16;
919 instr->opc
[all...]
H A Dir3_sched.c514 if ((instr->opc == OPC_META_INPUT) || (instr->opc == OPC_META_PHI)) {
629 if (instr->opc == OPC_META_PHI) {
H A Dir3_compiler_nir.c1398 opc_t opc = 0; local
1444 case nir_texop_tex: opc = OPC_SAM; break;
1445 case nir_texop_txb: opc = OPC_SAMB; break;
1446 case nir_texop_txl: opc = OPC_SAML; break;
1447 case nir_texop_txd: opc = OPC_SAMGQ; break;
1448 case nir_texop_txf: opc = OPC_ISAML; break;
1449 case nir_texop_lod: opc = OPC_GETLOD; break;
1481 if (ctx->unminify_coords && (opc == OPC_ISAML)) {
1502 if (ctx->array_index_add_half && (opc != OPC_ISAML))
1562 if (opc
[all...]
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir_emit_nvc0.cpp377 CodeEmitterNVC0::emitForm_A(const Instruction *i, uint64_t opc) argument
379 code[0] = opc;
380 code[1] = opc >> 32;
422 CodeEmitterNVC0::emitForm_B(const Instruction *i, uint64_t opc) argument
424 code[0] = opc;
425 code[1] = opc >> 32;
451 CodeEmitterNVC0::emitForm_S(const Instruction *i, uint32_t opc, bool pred) argument
453 code[0] = opc;
456 if (opc == 0x0d || opc
[all...]
/external/mesa3d/src/gallium/drivers/r600/
H A Dr600_isa.c560 unsigned opc; local
563 opc = op->opcode[isa->hw_class >> 1];
564 assert(opc != -1);
566 isa->alu_op3_map[opc] = i + 1;
568 isa->alu_op2_map[opc] = i + 1;
573 unsigned opc = op->opcode[isa->hw_class]; local
574 if ((op->flags & FF_GDS) || ((opc & 0xFF) != opc))
576 isa->fetch_map[opc] = i + 1;
581 unsigned opc local
[all...]
/external/mesa3d/src/gallium/drivers/freedreno/a2xx/
H A Dir-a2xx.c212 instr->opc = cf->cf_type;
291 fetch->opc = instr->fetch.opc;
293 if (instr->fetch.opc == VTX_FETCH) {
324 } else if (instr->fetch.opc == TEX_FETCH) {
351 ERROR_MSG("invalid fetch opc: %d\n", instr->fetch.opc);
453 * to always set scalar opc to MAXs if it is not used:
/external/wpa_supplicant_8/hostapd/
H A Dhlr_auc_gw.c86 u8 opc[16]; member in struct:milenage_parameters
127 " opc CHAR(32) NOT NULL,"
179 if (os_strcmp(col[i], "opc") == 0 && argv[i] &&
180 hexstr2bin(argv[i], m->opc, sizeof(m->opc))) {
448 hexstr2bin(pos, m->opc, 16)) {
541 pos += wpa_snprintf_hex(pos, end - pos, m->opc, 16);
621 gsm_milenage(m->opc, m->ki, _rand, sres, kc);
688 gsm_milenage(m->opc, m->ki, _rand, sres, kc);
763 milenage_generate(m->opc,
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/external/valgrind/VEX/priv/
H A Dguest_x86_toIR.c5558 UChar opc,
5579 switch (opc) {
5647 vex_printf("\n0x%x\n", opc);
5694 name, show_granularity ? nameMMXGran(opc & 3) : "",
5843 UChar opc = getIByte(delta); local
5849 switch (opc) {
5939 delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "padd", True );
5946 delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "padds", True );
5953 delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "paddus", True );
5961 delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "psu
5556 dis_MMXop_regmem_to_reg( UChar sorb, Int delta, UChar opc, const HChar* name, Bool show_granularity ) argument
8087 UChar opc, modrm, abyte, pre; local
[all...]
H A Dguest_amd64_toIR.c7177 UChar opc,
7198 switch (opc) {
7266 vex_printf("\n0x%x\n", (UInt)opc);
7313 name, show_granularity ? nameMMXGran(opc & 3) : "",
7462 UChar opc = getUChar(delta); local
7468 switch (opc) {
7608 delta = dis_MMXop_regmem_to_reg ( vbi, pfx, delta, opc, "padd", True );
7616 delta = dis_MMXop_regmem_to_reg ( vbi, pfx, delta, opc, "padds", True );
7623 delta = dis_MMXop_regmem_to_reg ( vbi, pfx, delta, opc, "paddus", True );
7631 delta = dis_MMXop_regmem_to_reg ( vbi, pfx, delta, opc, "psu
7174 dis_MMXop_regmem_to_reg( const VexAbiInfo* vbi, Prefix pfx, Long delta, UChar opc, const HChar* name, Bool show_granularity ) argument
10443 dis_CVTxSD2SI( const VexAbiInfo* vbi, Prefix pfx, Long delta, Bool isAvx, UChar opc, Int sz ) argument
10491 dis_CVTxSS2SI( const VexAbiInfo* vbi, Prefix pfx, Long delta, Bool isAvx, UChar opc, Int sz ) argument
12466 UChar opc = getUChar(delta); local
15410 UChar opc = getUChar(delta); local
15891 UChar opc = getUChar(delta); local
16411 UChar opc = getUChar(delta); local
16538 UChar opc = getUChar(delta); local
17936 UChar opc = getUChar(delta); local
18612 dis_PCMPISTRI_3A( UChar modrm, UInt regNoL, UInt regNoR, Long delta, UChar opc, UChar imm, HChar dis_buf[]) argument
19258 UChar opc = getUChar(delta); local
19954 UChar opc = getUChar(delta); delta++; local
21680 UChar opc = getUChar(delta); local
22636 UChar opc = getUChar(delta); local
22754 UChar opc = getUChar(delta); local
24066 UChar opc = getUChar(delta); local
28037 UChar opc = getUChar(delta); local
30283 dis_FMA4(Prefix pfx, Long delta, UChar opc, Bool* uses_vvvv, const VexAbiInfo* vbi ) argument
30403 UChar opc = getUChar(delta); local
[all...]
H A Dhost_mips_defs.c2113 static UChar *mkFormI(UChar * p, UInt opc, UInt rs, UInt rt, UInt imm) argument
2116 vassert(opc < 0x40);
2120 theInstr = ((opc << 26) | (rs << 21) | (rt << 16) | (imm));
2131 static UChar *mkFormR(UChar * p, UInt opc, UInt rs, UInt rt, UInt rd, UInt sa, argument
2137 vassert(opc < 0x40);
2143 theInstr = ((opc << 26) | (rs << 21) | (rt << 16) | (rd << 11) | (sa << 6) |
3176 UInt opc, sz = i->Min.Load.sz; local
3183 opc = 32;
3186 opc = 33;
3189 opc
3203 UInt opc, sz = i->Min.Load.sz; local
3233 UInt opc, sz = i->Min.Store.sz; local
3260 UInt opc, sz = i->Min.Store.sz; local
[all...]
H A Dhost_x86_defs.c2132 UInt irno, opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc; local
2197 opc = opc_rr = subopc_imm = opc_imma = 0;
2199 case Xalu_ADC: opc = 0x13; opc_rr = 0x11;
2201 case Xalu_ADD: opc = 0x03; opc_rr = 0x01;
2203 case Xalu_SUB: opc = 0x2B; opc_rr = 0x29;
2205 case Xalu_SBB: opc = 0x1B; opc_rr = 0x19;
2207 case Xalu_AND: opc = 0x23; opc_rr = 0x21;
2209 case Xalu_XOR: opc = 0x33; opc_rr = 0x31;
2211 case Xalu_OR: opc = 0x0B; opc_rr = 0x09;
2213 case Xalu_CMP: opc
[all...]
H A Dhost_amd64_defs.c2455 UInt /*irno,*/ opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc; local
2567 opc = opc_rr = subopc_imm = opc_imma = 0;
2569 case Aalu_ADC: opc = 0x13; opc_rr = 0x11;
2571 case Aalu_ADD: opc = 0x03; opc_rr = 0x01;
2573 case Aalu_SUB: opc = 0x2B; opc_rr = 0x29;
2575 case Aalu_SBB: opc = 0x1B; opc_rr = 0x19;
2577 case Aalu_AND: opc = 0x23; opc_rr = 0x21;
2579 case Aalu_XOR: opc = 0x33; opc_rr = 0x31;
2581 case Aalu_OR: opc = 0x0B; opc_rr = 0x09;
2583 case Aalu_CMP: opc
[all...]
/external/freetype/src/truetype/
H A Dttobjs.h164 FT_UInt opc; /* function #, or instruction code */ member in struct:TT_DefRecord_
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAsmBackend.cpp431 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 local
434 opc = 2; // 0b0010
441 return ARM_AM::getSOImmVal(Value) | (opc << 21);
446 unsigned opc = 0; local
449 opc = 5;
452 uint32_t out = (opc << 21);
/external/llvm/lib/IR/
H A DConstantFold.cpp76 unsigned opc, ///< opcode of the second cast constant expression
82 assert(CastInst::isCast(opc) && "Invalid cast opcode");
88 Instruction::CastOps secondOp = Instruction::CastOps(opc);
522 Constant *llvm::ConstantFoldCastInstruction(unsigned opc, Constant *V, argument
528 if (opc == Instruction::ZExt || opc == Instruction::SExt ||
529 opc == Instruction::UIToFP || opc == Instruction::SIToFP)
535 opc != Instruction::AddrSpaceCast)
543 if (unsigned newOpc = foldConstantCastPair(opc, C
75 foldConstantCastPair( unsigned opc, ConstantExpr *Op, Type *DstTy ) argument
[all...]
/external/llvm/include/llvm/TableGen/
H A DRecord.h758 UnOpInit(UnaryOp opc, Init *lhs, RecTy *Type) argument
759 : OpInit(IK_UnOpInit, Type, opc), LHS(lhs) {}
768 static UnOpInit *get(UnaryOp opc, Init *lhs, RecTy *Type);
807 BinOpInit(BinaryOp opc, Init *lhs, Init *rhs, RecTy *Type) : argument
808 OpInit(IK_BinOpInit, Type, opc), LHS(lhs), RHS(rhs) {}
817 static BinOpInit *get(BinaryOp opc, Init *lhs, Init *rhs,
860 TernOpInit(TernaryOp opc, Init *lhs, Init *mhs, Init *rhs, argument
862 OpInit(IK_TernOpInit, Type, opc), LHS(lhs), MHS(mhs), RHS(rhs) {}
871 static TernOpInit *get(TernaryOp opc, Init *lhs,
/external/swiftshader/third_party/LLVM/include/llvm/TableGen/
H A DRecord.h916 UnOpInit(UnaryOp opc, Init *lhs, RecTy *Type) argument
917 : OpInit(Type), Opc(opc), LHS(lhs) {}
923 static UnOpInit *get(UnaryOp opc, Init *lhs, RecTy *Type);
959 BinOpInit(BinaryOp opc, Init *lhs, Init *rhs, RecTy *Type) : argument
960 OpInit(Type), Opc(opc), LHS(lhs), RHS(rhs) {}
966 static BinOpInit *get(BinaryOp opc, Init *lhs, Init *rhs,
1008 TernOpInit(TernaryOp opc, Init *lhs, Init *mhs, Init *rhs, argument
1010 OpInit(Type), Opc(opc), LHS(lhs), MHS(mhs), RHS(rhs) {}
1016 static TernOpInit *get(TernaryOp opc, Init *lhs,
/external/clang/lib/StaticAnalyzer/Core/
H A DSimpleSValBuilder.cpp436 BinaryOperator::Opcode opc = symIntExpr->getOpcode(); local
437 switch (opc) {
473 opc = BinaryOperator::negateComparisonOp(opc);
474 return makeNonLoc(symIntExpr->getLHS(), opc,
/external/pcre/dist2/src/sljit/
H A DsljitNativeTILEGX_64.c524 void insert_nop(tilegx_mnemonic opc, int line) argument
530 opcode = &tilegx_opcodes[opc];
566 tilegx_mnemonic opc = inst_buf[0].opcode->can_bundle local
568 insert_nop(opc, __LINE__);
744 static sljit_s32 push_4_buffer(struct sljit_compiler *compiler, tilegx_mnemonic opc, int op0, int op1, int op2, int op3, int line) argument
749 const struct tilegx_opcode* opcode = &tilegx_opcodes[opc];
764 static sljit_s32 push_3_buffer(struct sljit_compiler *compiler, tilegx_mnemonic opc, int op0, int op1, int op2, int line) argument
769 const struct tilegx_opcode* opcode = &tilegx_opcodes[opc];
777 switch (opc) {
816 printf("unrecoginzed opc
825 push_2_buffer(struct sljit_compiler *compiler, tilegx_mnemonic opc, int op0, int op1, int line) argument
870 push_0_buffer(struct sljit_compiler *compiler, tilegx_mnemonic opc, int line) argument
886 push_jr_buffer(struct sljit_compiler *compiler, tilegx_mnemonic opc, int op0, int line) argument
[all...]
/external/swiftshader/third_party/LLVM/lib/VMCore/
H A DConstantsContext.h231 CompareConstantExpr(Type *ty, Instruction::OtherOps opc, argument
233 : ConstantExpr(ty, opc, &Op<0>(), 2), predicate(pred) {
304 ExprMapKeyType(unsigned opc, argument
309 : opcode(opc), subclassoptionaldata(optionalflags), subclassdata(flags),

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