/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_clip_unfilled.c | 52 struct brw_reg e = c->reg.tmp0; 53 struct brw_reg f = c->reg.tmp1; 55 struct brw_reg v0 = byte_offset(c->reg.vertex[0], hpos_offset); 56 struct brw_reg v1 = byte_offset(c->reg.vertex[1], hpos_offset); 57 struct brw_reg v2 = byte_offset(c->reg.vertex[2], hpos_offset); 94 brw_MUL(p, c->reg.dir, c->reg.dir, vec4(e)); 114 get_element(c->reg.dir, 2), 151 get_element(c->reg.dir, 2), 162 byte_offset(c->reg [all...] |
/external/mesa3d/src/gallium/drivers/r300/compiler/ |
H A D | radeon_dataflow_swizzles.c | 102 struct rc_src_register *reg) 108 if (!rc_src_reg_is_immediate(c, reg->File, reg->Index)) { 115 unsigned swz = GET_SWZ(reg->Swizzle, chan); 125 new_swizzle = reg->Swizzle; 135 unsigned chan_swz = GET_SWZ(reg->Swizzle, chan); 327 swz3 = GET_SWZ(reg->Swizzle, 3); 332 unsigned old_swz = GET_SWZ(reg->Swizzle, chan); 337 * reg->Swizzle == XWZW 369 unsigned old_swz = GET_SWZ(reg 101 try_rewrite_constant(struct radeon_compiler *c, struct rc_src_register *reg) argument 434 struct rc_src_register *reg = &inst->U.I.SrcReg[src]; local [all...] |
H A D | r300_fragprog_swizzle.c | 107 static int r300_swizzle_is_native(rc_opcode opcode, struct rc_src_register reg) argument 117 if (reg.Abs || reg.Negate) 121 unsigned int swz = GET_SWZ(reg.Swizzle, j); 134 if (GET_SWZ(reg.Swizzle, j) != RC_SWIZZLE_UNUSED) 137 if ((reg.Negate & relevant) && ((reg.Negate & relevant) != relevant)) 140 sd = lookup_native_swizzle(reg.Swizzle); 141 if (!sd || (reg.File == RC_FILE_PRESUB && sd->srcp_stride == 0))
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/external/capstone/arch/Mips/ |
H A D | MipsMapping.h | 10 const char *Mips_reg_name(csh handle, unsigned int reg);
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/external/capstone/arch/SystemZ/ |
H A D | SystemZMapping.h | 10 const char *SystemZ_reg_name(csh handle, unsigned int reg);
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/external/capstone/arch/XCore/ |
H A D | XCoreMapping.h | 10 const char *XCore_reg_name(csh handle, unsigned int reg);
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/external/kernel-headers/original/uapi/asm-x86/asm/ |
H A D | mtrr.h | 92 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) 93 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
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/external/libxaac/decoder/ |
H A D | ixheaacd_adts_crc_check.h | 28 ia_bit_buf_struct *it_bit_buff_src, WORD32 reg);
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/external/mesa3d/src/gallium/drivers/freedreno/ir3/ |
H A D | ir3.c | 81 static uint32_t reg(struct ir3_register *reg, struct ir3_info *info, argument 86 if (reg->flags & ~valid_flags) { 88 reg->flags, valid_flags); 91 if (!(reg->flags & IR3_REG_R)) 94 if (reg->flags & IR3_REG_IMMED) { 95 val.iim_val = reg->iim_val; 100 if (reg->flags & IR3_REG_RELATIV) { 101 components = reg->size; 102 val.idummy10 = reg 610 struct ir3_register *reg = local 696 struct ir3_register *reg = instr->regs[i]; local 709 struct ir3_register *reg = reg_create(shader, num, flags); local 717 ir3_reg_clone(struct ir3 *shader, struct ir3_register *reg) argument [all...] |
/external/valgrind/VEX/priv/ |
H A D | host_generic_regs.c | 107 HReg reg = univ->regs[i]; local 108 vassert(!hregIsInvalid(reg)); 109 vassert(!hregIsVirtual(reg)); 110 vassert(hregIndex(reg) == i); 113 HReg reg = univ->regs[i]; local 114 vassert(hregIsInvalid(reg)); 120 /*--- Helpers for recording reg usage (for reg-alloc) ---*/ 162 create duplicate entries -- each reg is only mentioned once. 164 void addHRegUse ( HRegUsage* tab, HRegMode mode, HReg reg ) [all...] |
/external/llvm/lib/Target/BPF/ |
H A D | BPFRegisterInfo.cpp | 68 unsigned reg = MI.getOperand(i - 1).getReg(); local 69 BuildMI(MBB, ++II, DL, TII.get(BPF::ADD_ri), reg) 70 .addReg(reg) 85 unsigned reg = MI.getOperand(i - 1).getReg(); local 87 BuildMI(MBB, ++II, DL, TII.get(BPF::MOV_rr), reg) 89 BuildMI(MBB, II, DL, TII.get(BPF::ADD_ri), reg) 90 .addReg(reg)
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcFrameLowering.cpp | 291 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) 292 if (!MRI->reg_nodbg_empty(reg)) 295 for (unsigned reg = SP::L0; reg <= SP::L7; ++reg) 296 if (!MRI->reg_nodbg_empty(reg)) 317 for (unsigned reg = SP::I0; reg < [all...] |
/external/clang/test/CodeGen/ |
H A D | builtins-systemz.c | 12 void test_htm1(struct __htm_tdb *tdb, int reg, int *mem, uint64_t *mem64) { argument 66 __builtin_tabort (reg); 80 __builtin_non_tx_store (mem64, (uint64_t)reg); 90 __builtin_non_tx_store (&g, reg); 101 __builtin_tx_assist (reg);
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/external/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
H A D | fd2_draw.c | 130 uint32_t reg, colr = 0; local 167 reg = 0; 169 reg |= A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE; 173 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xe); 175 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0x1); 179 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xf); 186 OUT_RING(ring, reg); 190 reg = 0; 194 reg = (((uint32_t)(0xffffff * depth)) << 8) | 198 reg [all...] |
/external/mesa3d/src/gallium/drivers/vc4/ |
H A D | vc4_opt_algebraic.c | 63 is_constant_value(struct vc4_compile *c, struct qreg reg, argument 66 if (reg.file == QFILE_UNIF && 67 !reg.pack && 68 c->uniform_contents[reg.index] == QUNIFORM_CONSTANT && 69 c->uniform_data[reg.index] == val) { 73 if (reg.file == QFILE_SMALL_IMM && reg.index == val) 80 is_zero(struct vc4_compile *c, struct qreg reg) argument 82 reg = qir_follow_movs(c, reg); 87 is_1f(struct vc4_compile *c, struct qreg reg) argument [all...] |
H A D | vc4_qir.c | 347 qir_print_reg(struct vc4_compile *c, struct qreg reg, bool write) argument 368 switch (reg.file) { 375 fprintf(stderr, "0x%08x (%f)", reg.index, uif(reg.index)); 379 if ((int)reg.index >= -16 && (int)reg.index <= 15) 380 fprintf(stderr, "%d", reg.index); 382 fprintf(stderr, "%f", uif(reg.index)); 390 reg.index / 4, reg 523 struct qreg reg; local 672 qir_follow_movs(struct vc4_compile *c, struct qreg reg) argument [all...] |
/external/syslinux/gpxe/src/drivers/net/ |
H A D | prism2.c | 175 static inline UINT16 hfa384x_getreg( hfa384x_t *hw, UINT reg ) 178 return inw ( hw->iobase + reg ); 180 return readw ( hw->membase + reg ); 185 static inline void hfa384x_setreg( hfa384x_t *hw, UINT16 val, UINT reg ) 188 outw ( val, hw->iobase + reg ); 190 writew ( val, hw->membase + reg ); 199 static inline UINT16 hfa384x_getreg_noswap( hfa384x_t *hw, UINT reg ) 201 return hfa384x_getreg ( hw, reg ); 203 static inline void hfa384x_setreg_noswap( hfa384x_t *hw, UINT16 val, UINT reg ) 205 hfa384x_setreg ( hw, val, reg ); 232 UINT16 reg = 0; local 295 UINT16 reg; local 342 UINT16 reg = 0; local 581 UINT16 reg; local 603 UINT16 reg; local [all...] |
/external/linux-kselftest/tools/testing/selftests/powerpc/ptrace/ |
H A D | ptrace.h | 30 #include "reg.h" 109 unsigned long *reg; local 112 reg = malloc(sizeof(unsigned long)); 113 if (!reg) { 117 iov.iov_base = (u64 *) reg; 126 out[0] = *reg; 134 out[1] = *reg; 142 out[2] = *reg; 144 free(reg); 147 free(reg); 155 unsigned long *reg; local 198 unsigned long *reg; local 246 unsigned long *reg; local [all...] |
/external/mesa3d/src/gallium/drivers/ilo/core/ |
H A D | ilo_builder_mi.h | 78 uint32_t reg, uint32_t val) 85 assert(reg % 4 == 0); 90 dw[1] = reg; 95 gen6_MI_STORE_REGISTER_MEM(struct ilo_builder *builder, uint32_t reg, argument 105 assert(reg % 4 == 0 && bo_offset % 4 == 0); 110 dw[1] = reg; 170 gen7_MI_LOAD_REGISTER_MEM(struct ilo_builder *builder, uint32_t reg, argument 179 assert(reg % 4 == 0 && bo_offset % 4 == 0); 184 dw[1] = reg; 77 gen6_MI_LOAD_REGISTER_IMM(struct ilo_builder *builder, uint32_t reg, uint32_t val) argument
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | CalcSpillWeights.cpp | 52 if (TargetRegisterInfo::isVirtualRegister(li.reg)) 58 // Return the preferred allocation register for reg, given a COPY instruction. 59 static unsigned copyHint(const MachineInstr *mi, unsigned reg, argument 63 if (mi->getOperand(0).getReg() == reg) { 79 const TargetRegisterClass *rc = mri.getRegClass(reg); 85 // reg:sub should match the physreg hreg. 104 bool noHint = mri.getRegAllocationHint(li.reg).first != 0; 109 for (MachineRegisterInfo::reg_iterator I = mri.reg_begin(li.reg); 128 tie(reads, writes) = mi->readsWritesVirtualRegister(li.reg); 141 unsigned hint = copyHint(mi, li.reg, tr [all...] |
/external/syslinux/com32/elflink/ldlinux/ |
H A D | chainboot.c | 47 com32sys_t reg; local 61 reg.eax.l = max; 62 reg.ebx.l = 0; 63 reg.edx.w[0] = 0; 64 reg.edi.l = (uint32_t)buf; 65 reg.ebp.l = -1; /* XXX: limit? */ 66 reg.esi.w[0] = rv; 68 pm_load_high(®); 70 size = reg.edi.l - (unsigned long)buf;
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/external/libunwind/src/x86/ |
H A D | Ginit.c | 50 tdep_uc_addr (ucontext_t *uc, int reg) argument 52 return x86_r_uc_addr (uc, reg); 193 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write, argument 199 if (unw_is_fpreg (reg)) 202 if (!(addr = x86_r_uc_addr (uc, reg))) 208 Debug (12, "%s <- %x\n", unw_regname (reg), *val); 213 Debug (12, "%s -> %x\n", unw_regname (reg), *val); 218 Debug (1, "bad register number %u\n", reg); 223 access_fpreg (unw_addr_space_t as, unw_regnum_t reg, unw_fpreg_t *val, argument 229 if (!unw_is_fpreg (reg)) [all...] |
/external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
H A D | nv50_ir_peephole.cpp | 45 if (defExists(0) && def(0).rep()->reg.data.id < 0) { 47 if (def(d).rep()->reg.data.id >= 0) 74 if (getDef(d)->refCount() || getDef(d)->reg.data.id >= 0) 110 if (mov->getDef(0)->reg.data.id < 0 && si && si->op != OP_PHI) { 254 if (i->op == OP_PFETCH) // pfetch expects arg1 to be a reg 308 !targ->insnCanLoadOffset(i, s, imm.reg.data.s32)) 312 i->src(s).get()->reg.data.offset += imm.reg.data.u32; 316 !targ->insnCanLoadOffset(i, s, -imm.reg.data.s32)) 320 i->src(s).get()->reg [all...] |
/external/mesa3d/src/compiler/nir/ |
H A D | nir_validate.c | 134 validate_assert(state, src->reg.reg != NULL); 137 entry = _mesa_hash_table_search(state->regs, src->reg.reg); 149 if (!src->reg.reg->is_global) { 154 validate_assert(state, (src->reg.reg->num_array_elems == 0 || 155 src->reg.base_offset < src->reg 853 prevalidate_reg_decl(nir_register *reg, bool is_global, validate_state *state) argument 882 postvalidate_reg_decl(nir_register *reg, validate_state *state) argument [all...] |
/external/mesa3d/src/gallium/drivers/etnaviv/ |
H A D | etnaviv_asm.c | 50 uni_reg = src->reg; 52 if (uni_rgroup != src->rgroup || uni_reg != src->reg) { 76 VIV_ISA_WORD_0_DST_REG(inst->dst.reg) | 82 VIV_ISA_WORD_1_SRC0_REG(inst->src[0].reg) | 90 VIV_ISA_WORD_2_SRC1_REG(inst->src[1].reg) | 98 VIV_ISA_WORD_3_SRC2_REG(inst->src[2].reg) |
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