/external/v8/src/ic/s390/ |
H A D | ic-s390.cc | 103 Register reg; local 104 reg.reg_code = instr_at_patch & 0xf; 106 patcher.masm()->TestIfSmi(reg); 111 patcher.masm()->CmpP(reg, reg);
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/external/libunwind/src/aarch64/ |
H A D | Gresume.c | 138 int reg; local 142 for (reg = 0; reg <= UNW_AARCH64_PSTATE; ++reg) 144 Debug (16, "copying %s %d\n", unw_regname (reg), reg); 145 if (unw_is_fpreg (reg)) 147 if (tdep_access_fpreg (c, reg, &fpval, 0) >= 0) 148 as->acc.access_fpreg (as, reg, &fpval, 1, arg); 152 if (tdep_access_reg (c, reg, [all...] |
/external/syslinux/gpxe/src/drivers/bus/ |
H A D | pci.c | 45 * @v reg PCI register number 55 static unsigned long pci_bar ( struct pci_device *pci, unsigned int reg ) { 59 pci_read_config_dword ( pci, reg, &low ); 62 pci_read_config_dword ( pci, reg + 4, &high ); 80 * @v reg PCI register number 90 unsigned long pci_bar_start ( struct pci_device *pci, unsigned int reg ) { 93 bar = pci_bar ( pci, reg ); 116 int reg; local 118 for ( reg = PCI_BASE_ADDRESS_0; reg < [all...] |
/external/vixl/src/aarch32/ |
H A D | instructions-aarch32.h | 128 bool IsSameFormat(CPURegister reg) { 129 return (value_ & ~kCodeMask) == (reg.value_ & ~kCodeMask); 149 std::ostream& operator<<(std::ostream& os, const Register reg); 169 const RegisterOrAPSR_nzcv reg) { 170 if (reg.IsAPSR_nzcv()) return os << "APSR_nzcv"; 171 return os << reg.AsRegister(); 215 inline std::ostream& operator<<(std::ostream& os, const SRegister reg) { 216 return os << "s" << reg.GetCode(); 245 inline std::ostream& operator<<(std::ostream& os, const DRegister reg) { 246 return os << "d" << reg [all...] |
/external/toybox/toys/posix/ |
H A D | sed.c | 465 regex_t *reg = get_regex(command, command->arg1); local 469 while (!regexec0(reg, rline, rlen, 10, match, mflags)) { 722 char *line, *reg, c, *errstart; local 737 reg = (char *)command; 738 reg += command->arg1 + strlen(reg + command->arg1); 767 reg = toybuf + sizeof(struct sedcmd); 784 xregcomp((void *)reg, s, (toys.optflags & FLAG_r)*REG_EXTENDED); 785 command->rmatch[i] = reg-toybuf; 786 reg [all...] |
/external/capstone/arch/XCore/ |
H A D | XCoreInstPrinter.c | 69 MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id; 130 MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id; 142 MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id; 150 static void set_mem_access(MCInst *MI, bool status, int reg) argument 157 if (reg != 0xffff && reg != -0xffff) { 159 if (reg) { 160 MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)reg; 171 MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg; 174 if (reg > 191 unsigned reg; local [all...] |
/external/v8/src/x64/ |
H A D | assembler-x64-inl.h | 92 void Assembler::emit_rex_64(Register reg, Register rm_reg) { argument 93 emit(0x48 | reg.high_bit() << 2 | rm_reg.high_bit()); 97 void Assembler::emit_rex_64(XMMRegister reg, Register rm_reg) { argument 98 emit(0x48 | (reg.code() & 0x8) >> 1 | rm_reg.code() >> 3); 102 void Assembler::emit_rex_64(Register reg, XMMRegister rm_reg) { argument 103 emit(0x48 | (reg.code() & 0x8) >> 1 | rm_reg.code() >> 3); 107 void Assembler::emit_rex_64(Register reg, const Operand& op) { argument 108 emit(0x48 | reg.high_bit() << 2 | op.rex_); 112 void Assembler::emit_rex_64(XMMRegister reg, const Operand& op) { argument 113 emit(0x48 | (reg 128 emit_rex_32(Register reg, Register rm_reg) argument 133 emit_rex_32(Register reg, const Operand& op) argument 148 emit_optional_rex_32(Register reg, Register rm_reg) argument 154 emit_optional_rex_32(Register reg, const Operand& op) argument 160 emit_optional_rex_32(XMMRegister reg, const Operand& op) argument 166 emit_optional_rex_32(XMMRegister reg, XMMRegister base) argument 172 emit_optional_rex_32(XMMRegister reg, Register base) argument 178 emit_optional_rex_32(Register reg, XMMRegister base) argument 198 emit_vex3_byte1(XMMRegister reg, XMMRegister rm, LeadingOpcode m) argument 206 emit_vex3_byte1(XMMRegister reg, const Operand& rm, LeadingOpcode m) argument 214 emit_vex2_byte1(XMMRegister reg, XMMRegister v, VectorLength l, SIMDPrefix pp) argument 228 emit_vex_prefix(XMMRegister reg, XMMRegister vreg, XMMRegister rm, VectorLength l, SIMDPrefix pp, LeadingOpcode mm, VexW w) argument 242 emit_vex_prefix(Register reg, Register vreg, Register rm, VectorLength l, SIMDPrefix pp, LeadingOpcode mm, VexW w) argument 252 emit_vex_prefix(XMMRegister reg, XMMRegister vreg, const Operand& rm, VectorLength l, SIMDPrefix pp, LeadingOpcode mm, VexW w) argument 266 emit_vex_prefix(Register reg, Register vreg, const Operand& rm, VectorLength l, SIMDPrefix pp, LeadingOpcode mm, VexW w) argument [all...] |
/external/mmc-utils/ |
H A D | mmc_cmds.c | 101 __u8 reg; local 109 reg = ext_csd[EXT_CSD_BOOT_WP]; 110 printf("Boot Area Write protection [BOOT_WP]: 0x%02x\n", reg); 112 if (reg & EXT_CSD_BOOT_WP_B_PWR_WP_DIS) 118 if (reg & EXT_CSD_BOOT_WP_B_PERM_WP_DIS) 124 if (reg & EXT_CSD_BOOT_WP_B_PWR_WP_EN) 126 else if (reg & EXT_CSD_BOOT_WP_B_PERM_WP_EN) 995 __u8 ext_csd[512], ext_csd_rev, reg; local 1056 reg = ext_csd[EXT_CSD_S_CMD_SET]; 1057 printf("Card Supported Command sets [S_CMD_SET: 0x%02x]\n", reg); [all...] |
/external/tensorflow/tensorflow/contrib/lite/ |
H A D | interpreter_test.cc | 209 TfLiteRegistration reg = {nullptr, nullptr, nullptr, nullptr}; local 219 interpreter.AddNodeWithParameters({0, 1}, {2, 3}, nullptr, 0, nullptr, ®); 220 interpreter.AddNodeWithParameters({2, 1}, {4, 5}, nullptr, 0, nullptr, ®); 221 interpreter.AddNodeWithParameters({4, 3}, {6, 7}, nullptr, 0, nullptr, ®); 222 interpreter.AddNodeWithParameters({6, 5}, {8}, nullptr, 0, nullptr, ®); 223 interpreter.AddNodeWithParameters({8, 7}, {9}, nullptr, 0, nullptr, ®); 349 TfLiteRegistration reg = {nullptr, nullptr, nullptr, nullptr}; local 350 reg.init = [](TfLiteContext* context, const char*, size_t) -> void* { 355 reg.free = [](TfLiteContext* context, void* buffer) { 358 reg 508 TfLiteRegistration reg = {nullptr, nullptr, nullptr, nullptr}; local 590 TfLiteRegistration reg = {nullptr, nullptr, nullptr, nullptr}; local 694 TfLiteRegistration reg = {nullptr, nullptr, nullptr, nullptr}; local 740 TfLiteRegistration reg = AddOpRegistration(); local 795 TfLiteRegistration reg = {nullptr}; local [all...] |
/external/lzma/Asm/x86/ |
H A D | AesOpt.asm | 21 MY_PROLOG macro reg:req
35 movdqa reg, [r1]
75 CBC_DEC_UPDATE macro reg, offs
76 pxor reg, xmm6
78 movdqa [rD + offs], reg
170 XOR_UPD_1 macro reg, offs
171 pxor reg, [rD + offs]
174 XOR_UPD_2 macro reg, offs
175 movdqa [rD + offs], reg
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/external/v8/src/ppc/ |
H A D | disasm-ppc.cc | 68 void PrintRegister(int reg); 69 void PrintDRegister(int reg); 116 void Decoder::PrintRegister(int reg) { argument 117 Print(converter_.NameOfCPURegister(reg)); 122 void Decoder::PrintDRegister(int reg) { argument 123 Print(GetRegConfig()->GetDoubleRegisterName(reg)); 155 int reg = instr->RTValue(); local 156 PrintRegister(reg); 159 int reg = instr->RAValue(); local 160 PrintRegister(reg); 163 int reg = instr->RBValue(); local 179 int reg = -1; local [all...] |
/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_vec4.cpp | 68 src_reg::src_reg(struct ::brw_reg reg) : argument 69 backend_reg(reg) 75 src_reg::src_reg(const dst_reg ®) : argument 76 backend_reg(reg) 78 this->reladdr = reg.reladdr; 79 this->swizzle = brw_swizzle_for_mask(reg.writemask); 125 dst_reg::dst_reg(struct ::brw_reg reg) : argument 126 backend_reg(reg) 132 dst_reg::dst_reg(const src_reg ®) : argument 133 backend_reg(reg) 622 int reg = inst->src[i].nr; local 649 int reg = inst->src[0].nr; local 1008 int reg = inst->src[i].nr + inst->src[i].offset / REG_SIZE; local 1027 int reg = inst->dst.nr + inst->dst.offset / REG_SIZE; local 1442 unsigned reg = alloc.allocate(1); local 1671 struct brw_reg reg; local 1715 struct brw_reg reg = local 1769 setup_uniforms(int reg) argument 1802 int reg = 0; local 1945 struct brw_reg reg; local 2013 struct brw_reg reg; local 2473 src_reg reg = inst->src[arg]; local [all...] |
/external/mesa3d/src/compiler/nir/ |
H A D | nir_clone.c | 117 remap_reg(clone_state *state, const nir_register *reg) argument 119 return _lookup_ptr(state, reg, reg->is_global); 192 clone_register(clone_state *state, const nir_register *reg) argument 195 add_remap(state, nreg, reg); 197 nreg->num_components = reg->num_components; 198 nreg->bit_size = reg->bit_size; 199 nreg->num_array_elems = reg->num_array_elems; 200 nreg->index = reg->index; 201 nreg->name = ralloc_strdup(nreg, reg [all...] |
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ |
H A D | ir3.h | 92 * the component is in the low two bits of the reg #, so 248 * result of moving a const to a reg would have a low cost, so to 413 unsigned reg; /* base physical reg */ member in struct:ir3_array 476 struct ir3_register *reg); 495 struct ir3_register *reg) 499 if (reg == instr->regs[i]) 518 static inline uint32_t reg_num(struct ir3_register *reg) argument 520 return reg->num >> 2; 523 static inline uint32_t reg_comp(struct ir3_register *reg) argument 494 ir3_instr_regno(struct ir3_instruction *instr, struct ir3_register *reg) argument 683 ssa(struct ir3_register *reg) argument 1113 struct ir3_register *reg; local 1149 regmask_idx(struct ir3_register *reg) argument 1163 regmask_set(regmask_t *regmask, struct ir3_register *reg) argument 1188 regmask_set_if_not(regmask_t *a, struct ir3_register *reg, regmask_t *b) argument 1206 regmask_get(regmask_t *regmask, struct ir3_register *reg) argument [all...] |
/external/mesa3d/src/gallium/drivers/r300/ |
H A D | r300_vs.c | 111 int i, reg = 0; local 121 c->code->outputs[outputs->pos] = reg++; 128 c->code->outputs[outputs->psize] = reg++; 134 * pretend it does by skipping output index reg so the colors 141 c->code->outputs[outputs->color[i]] = reg++; 144 reg++; 151 c->code->outputs[outputs->bcolor[i]] = reg++; 153 reg++; 160 c->code->outputs[outputs->generic[i]] = reg++; 166 c->code->outputs[outputs->fog] = reg [all...] |
/external/mesa3d/src/mesa/x86/rtasm/ |
H A D | x86sse.c | 92 struct x86_reg reg, 97 assert(reg.mod == mod_REG); 100 val |= reg.idx << 3; /* reg field */ 177 struct x86_reg reg; local 179 reg.file = file; 180 reg.idx = idx; 181 reg.mod = mod_REG; 182 reg.disp = 0; 184 return reg; 91 emit_modrm( struct x86_function *p, struct x86_reg reg, struct x86_reg regmem ) argument 187 x86_make_disp( struct x86_reg reg, int disp ) argument 295 x86_call( struct x86_function *p, struct x86_reg reg) argument [all...] |
/external/tensorflow/tensorflow/python/keras/_impl/keras/wrappers/ |
H A D | scikit_learn_test.py | 85 def assert_regression_works(reg): 93 reg.fit(x_train, y_train, batch_size=BATCH_SIZE, epochs=EPOCHS) 95 score = reg.score(x_train, y_train, batch_size=BATCH_SIZE) 98 preds = reg.predict(x_test, batch_size=BATCH_SIZE) 148 reg = keras.wrappers.scikit_learn.KerasRegressor( 154 assert_regression_works(reg) 164 reg = keras.wrappers.scikit_learn.KerasRegressor( variable in class:ScikitLearnAPIWrapperTest.test_regression_class_build_fn.ClassBuildFnReg 170 assert_regression_works(reg) 180 reg = InheritClassBuildFnReg( variable in class:ScikitLearnAPIWrapperTest.test_regression_inherit_class_build_fn.InheritClassBuildFnReg 186 assert_regression_works(reg) [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | RegAllocBasic.cpp | 202 unsigned reg = liItr->first; local 203 if (TargetRegisterInfo::isPhysicalRegister(reg)) continue; 204 if (!VRM->hasPhys(reg)) continue; // spilled? 205 unsigned PhysReg = VRM->getPhys(reg); 206 if (!unionVRegs[PhysReg].test(reg)) { 207 dbgs() << "LiveVirtReg " << reg << " not in union " << 241 // Cache an interferece query for each physical reg 277 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) 279 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); 280 VRM->assignVirt2Phys(VirtReg.reg, PhysRe [all...] |
/external/v8/src/ic/ |
H A D | handler-compiler.cc | 89 Register reg = FrontendHeader(receiver(), name, &miss, RETURN_HOLDER); local 95 return reg; 103 Register reg = Frontend(name); local 104 GenerateLoadCallback(reg, callback); 218 Register reg = FrontendHeader(receiver(), it->name(), &miss, RETURN_HOLDER); local 223 reg = receiver(); 227 __ LoadWeakValue(reg, cell, &miss); 231 InterceptorVectorSlotPop(reg); 235 GenerateLoadInterceptorWithFollowup(it, reg); 237 GenerateLoadInterceptor(reg); 242 GenerateLoadCallback( Register reg, Handle<AccessorInfo> callback) argument 245 __ Move(ApiGetterDescriptor::HolderRegister(), reg); local 265 Register reg = local 282 __ Move(LoadFieldDescriptor::ReceiverRegister(), reg); local 300 receiver(), scratch2(), false, no_reg, reg, local [all...] |
/external/v8/src/interpreter/ |
H A D | bytecode-register-optimizer.cc | 18 RegisterInfo(Register reg, uint32_t equivalence_id, bool materialized, argument 20 : register_(reg), 40 // materialized and not register |reg|. The materialized equivalent 43 RegisterInfo* GetMaterializedEquivalentOtherThan(Register reg); 145 Register reg) { 148 if (visitor->materialized() && visitor->register_value() != reg) { 372 void BytecodeRegisterOptimizer::PrepareOutputRegister(Register reg) { argument 373 RegisterInfo* reg_info = GetRegisterInfo(reg); 391 Register BytecodeRegisterOptimizer::GetInputRegister(Register reg) { argument 392 RegisterInfo* reg_info = GetRegisterInfo(reg); 144 GetMaterializedEquivalentOtherThan( Register reg) argument 419 GrowRegisterMap(Register reg) argument 434 RegisterAllocateEvent(Register reg) argument [all...] |
/external/mesa3d/src/gallium/drivers/r600/ |
H A D | r600_pipe.h | 799 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) argument 801 assert(reg < R600_CONTEXT_REG_OFFSET); 804 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 811 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) argument 813 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 816 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 823 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) argument 825 assert(reg >= R600_CTL_CONST_OFFSET); 828 cb->buf[cb->num_dw++] = (reg 831 r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) argument 843 eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) argument 851 r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) argument 857 r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) argument 863 r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) argument 869 r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) argument 875 eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) argument 884 radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) argument 891 radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) argument 899 radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) argument 905 radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag) argument 914 radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) argument [all...] |
/external/tcpdump/ |
H A D | print-mpcp.c | 130 const struct mpcp_reg_t *reg; member in union:__anon25281 224 mpcp.reg = (const struct mpcp_reg_t *)tptr; 227 EXTRACT_16BITS(mpcp.reg->assigned_port), 228 bittok2str(mpcp_reg_flag_values, "Reserved", mpcp.reg->flags), 229 EXTRACT_16BITS(mpcp.reg->sync_time), 230 mpcp.reg->echoed_pending_grants));
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/external/capstone/bindings/ocaml/ |
H A D | test_arm64.ml | 27 | ARM64_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name handle reg); 39 | ARM64_OP_REG_MRS reg -> printf "\t\top[%d]: REG_MRS = %u\n" i reg; 40 | ARM64_OP_REG_MSR reg -> printf "\t\top[%d]: REG_MSR = %u\n" i reg;
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/external/capstone/bindings/python/ |
H A D | test_ppc.py | 29 print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) 44 if i.crx.reg != 0: 45 print("\t\t\toperands[%u].crx.reg: REG = %s" \ 46 % (c, insn.reg_name(i.crx.reg)))
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/external/clang/test/CodeGen/ |
H A D | sparcv9-abi.c | 64 struct reg { struct 69 struct reg f_reg(struct reg x) {
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