Searched refs:reg (Results 76 - 100 of 1462) sorted by relevance

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/external/v8/src/interpreter/
H A Dbytecode-register-optimizer.h76 // Prepares |reg| for being used as an output operand.
77 void PrepareOutputRegister(Register reg);
82 // Returns an equivalent register to |reg| to be used as an input operand.
83 Register GetInputRegister(Register reg);
97 void RegisterAllocateEvent(Register reg) override;
99 void RegisterListFreeEvent(RegisterList reg) override;
124 RegisterInfo* GetRegisterInfo(Register reg) { argument
125 size_t index = GetRegisterInfoTableIndex(reg);
129 RegisterInfo* GetOrCreateRegisterInfo(Register reg) { argument
130 size_t index = GetRegisterInfoTableIndex(reg);
134 NewRegisterInfo(Register reg) argument
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/external/mesa3d/src/gallium/drivers/freedreno/ir3/
H A Dir3_print.c100 static void print_reg_name(struct ir3_register *reg) argument
102 if ((reg->flags & (IR3_REG_FABS | IR3_REG_SABS)) &&
103 (reg->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT)))
105 else if (reg->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))
107 else if (reg->flags & (IR3_REG_FABS | IR3_REG_SABS))
110 if (reg->flags & IR3_REG_IMMED) {
111 printf("imm[%f,%d,0x%x]", reg->fim_val, reg->iim_val, reg->iim_val);
112 } else if (reg
161 struct ir3_register *reg = instr->regs[i]; local
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/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_clip_tri.c57 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
60 c->reg.fixed_planes = brw_vec4_grf(i, 0);
72 c->reg.vertex[j] = brw_vec4_grf(i, 0);
83 brw_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), brw_imm_f(0));
87 c->reg.t = brw_vec1_grf(i, 0);
88 c->reg.loopcount = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_D);
89 c->reg.nr_verts = retype(brw_vec1_grf(i, 2), BRW_REGISTER_TYPE_UD);
90 c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD);
91 c->reg.plane_equation = brw_vec4_grf(i, 4);
94 c->reg
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H A Dbrw_fs_combine_constants.cpp85 reg_link(fs_reg *reg) : reg(reg) {} argument
88 fs_reg *reg; member in struct:reg_link
92 link(void *mem_ctx, fs_reg *reg) argument
94 reg_link *l = new(mem_ctx) reg_link(reg);
270 fs_reg reg(VGRF, alloc.allocate(1));
271 reg.stride = 0;
281 ibld.MOV(reg, brw_imm_f(imm->val));
282 imm->nr = reg
296 fs_reg *reg = link->reg; local
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H A Dbrw_vec4_vs_visitor.cpp43 dst_reg *reg = new(mem_ctx) dst_reg(ATTR, VERT_ATTRIB_MAX); local
47 reg->writemask = WRITEMASK_X;
51 reg->writemask = WRITEMASK_Y;
56 reg->writemask = WRITEMASK_Z;
60 reg->writemask = WRITEMASK_W;
64 reg = new(mem_ctx) dst_reg(ATTR, VERT_ATTRIB_MAX + 1);
65 reg->writemask = WRITEMASK_X;
72 return reg;
104 vec4_vs_visitor::emit_urb_slot(dst_reg reg, int varying) argument
106 reg
130 emit_clip_distances(dst_reg reg, int offset) argument
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/external/libunwind/src/arm/
H A DGinit.c42 uc_addr (unw_tdep_context_t *uc, int reg) argument
44 if (reg >= UNW_ARM_R0 && reg < UNW_ARM_R0 + 16)
45 return &uc->regs[reg - UNW_ARM_R0];
53 tdep_uc_addr (unw_tdep_context_t *uc, int reg) argument
55 return uc_addr (uc, reg);
121 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write, argument
127 if (unw_is_fpreg (reg))
130 Debug (16, "reg = %s\n", unw_regname (reg));
152 access_fpreg(unw_addr_space_t as, unw_regnum_t reg, unw_fpreg_t *val, int write, void *arg) argument
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/external/libunwind/src/hppa/
H A DGinit.c44 uc_addr (ucontext_t *uc, int reg) argument
48 if ((unsigned) (reg - UNW_HPPA_GR) < 32)
49 addr = &uc->uc_mcontext.sc_gr[reg - UNW_HPPA_GR];
50 else if ((unsigned) (reg - UNW_HPPA_FR) < 32)
51 addr = &uc->uc_mcontext.sc_fr[reg - UNW_HPPA_FR];
60 _Uhppa_uc_addr (ucontext_t *uc, int reg) argument
62 return uc_addr (uc, reg);
134 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write, argument
140 if ((unsigned int) (reg - UNW_HPPA_FR) < 32)
143 addr = uc_addr (uc, reg);
165 access_fpreg(unw_addr_space_t as, unw_regnum_t reg, unw_fpreg_t *val, int write, void *arg) argument
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/external/libunwind/src/ia64/
H A DGget_save_loc.c34 unw_get_save_loc (unw_cursor_t *cursor, int reg, unw_save_loc_t *sloc) argument
43 switch (reg)
57 loc = c->loc[IA64_REG_R4 + (reg - (UNW_IA64_GR + 4))];
61 loc = c->loc[IA64_REG_NAT4 + (reg - (UNW_IA64_NAT + 4))];
62 reg_loc = c->loc[IA64_REG_R4 + (reg - (UNW_IA64_NAT + 4))];
63 nat_bitnr = c->nat_bitnr[reg - (UNW_IA64_NAT + 4)];
74 loc = c->loc[IA64_REG_F16 + (reg - (UNW_IA64_FR + 16))];
92 case UNW_IA64_GR + 32 ... UNW_IA64_GR + 127: /* stacked reg */
93 reg = rotate_gr (c, reg
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H A DGregs.c31 linux_scratch_loc (struct cursor *c, unw_regnum_t reg, uint8_t *nat_bitnr) argument
40 switch (reg)
46 *nat_bitnr = (reg - UNW_IA64_NAT);
52 addr += LINUX_SC_GR_OFF + 8 * (reg - UNW_IA64_GR);
56 addr += LINUX_SC_FR_OFF + 16 * (reg - UNW_IA64_FR);
78 addr += LINUX_SC_FR_OFF + 16 * (reg - UNW_IA64_FR);
90 if (unw_is_fpreg (reg))
91 return IA64_FPREG_LOC (c, reg);
93 return IA64_REG_LOC (c, reg);
101 if ((unsigned) (reg
223 hpux_scratch_loc(struct cursor *c, unw_regnum_t reg, uint8_t *nat_bitnr) argument
233 ia64_scratch_loc(struct cursor *c, unw_regnum_t reg, uint8_t *nat_bitnr) argument
360 tdep_access_reg(struct cursor *c, unw_regnum_t reg, unw_word_t *valp, int write) argument
562 tdep_access_fpreg(struct cursor *c, int reg, unw_fpreg_t *valp, int write) argument
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/external/mesa3d/src/gallium/drivers/svga/svgadump/
H A Dsvga_shader.h60 sh_reg_type( struct sh_reg reg )
62 return reg.type_lo | (reg.type_hi << 3);
73 struct sh_reg reg; member in struct:sh_def
80 struct sh_reg reg; member in struct:sh_defb
92 struct sh_reg reg; member in struct:sh_defi
142 sh_dstreg_type( struct sh_dstreg reg )
144 return reg.type_lo | (reg.type_hi << 3);
154 struct sh_dstreg reg; member in struct:sh_dcl
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/external/mesa3d/src/gallium/drivers/radeon/
H A Dr600_cs.h131 static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) argument
133 assert(reg < R600_CONTEXT_REG_OFFSET);
136 radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
139 static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) argument
141 radeon_set_config_reg_seq(cs, reg, 1);
145 static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) argument
147 assert(reg >= R600_CONTEXT_REG_OFFSET);
150 radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
153 static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) argument
155 radeon_set_context_reg_seq(cs, reg,
159 radeon_set_context_reg_idx(struct radeon_winsys_cs *cs, unsigned reg, unsigned idx, unsigned value) argument
170 radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) argument
178 radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) argument
184 radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) argument
192 radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) argument
198 radeon_set_uconfig_reg_idx(struct radeon_winsys_cs *cs, unsigned reg, unsigned idx, unsigned value) argument
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/external/libunwind/src/aarch64/
H A DGinit.c44 uc_addr (ucontext_t *uc, int reg) argument
46 if (reg >= UNW_AARCH64_X0 && reg <= UNW_AARCH64_V31)
47 return &uc->uc_mcontext.regs[reg];
55 tdep_uc_addr (ucontext_t *uc, int reg) argument
57 return uc_addr (uc, reg);
129 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write, argument
135 if (unw_is_fpreg (reg))
138 if (!(addr = uc_addr (uc, reg)))
144 Debug (12, "%s <- %lx\n", unw_regname (reg), *va
159 access_fpreg(unw_addr_space_t as, unw_regnum_t reg, unw_fpreg_t *val, int write, void *arg) argument
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H A Dregname.c100 unw_regname (unw_regnum_t reg) argument
102 if (reg < (unw_regnum_t) ARRAY_SIZE (regname) && regname[reg] != NULL)
103 return regname[reg];
/external/libunwind/src/sh/
H A DGinit.c43 uc_addr (ucontext_t *uc, int reg) argument
45 if (reg >= UNW_SH_R0 && reg <= UNW_SH_PR)
46 return &uc->uc_mcontext.gregs[reg];
54 tdep_uc_addr (ucontext_t *uc, int reg) argument
56 return uc_addr (uc, reg);
128 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write, argument
134 if (unw_is_fpreg (reg))
137 if (!(addr = uc_addr (uc, reg)))
143 Debug (12, "%s <- %x\n", unw_regname (reg), *va
158 access_fpreg(unw_addr_space_t as, unw_regnum_t reg, unw_fpreg_t *val, int write, void *arg) argument
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/external/mesa3d/src/mesa/drivers/dri/r200/
H A Dr200_vertprog.h145 #define VSF_ATTR_UNITY(reg) EASY_VSF_SOURCE(reg, ONE, ONE, ONE, ONE, ATTR, NONE)
146 #define VSF_UNITY(reg) EASY_VSF_SOURCE(reg, ONE, ONE, ONE, ONE, NONE, NONE)
149 #define VSF_REG(reg) EASY_VSF_SOURCE(reg, X, Y, Z, W, ATTR, NONE)
152 #define VSF_PARAM(reg) EASY_VSF_SOURCE(reg, X, Y, Z, W, PARAM, NONE)
155 #define VSF_TMP(reg) EASY_VSF_SOURCE(reg,
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/external/libunwind/src/mips/
H A DGregs.c30 tdep_access_reg (struct cursor *c, unw_regnum_t reg, unw_word_t *valp, argument
35 switch (reg)
69 loc = c->dwarf.loc[reg - UNW_MIPS_R0];
73 loc = c->dwarf.loc[reg];
85 Debug (1, "bad register number %u\n", reg);
98 tdep_access_fpreg (struct cursor *c, unw_regnum_t reg, unw_fpreg_t *valp, argument
101 Debug (1, "bad register number %u\n", reg);
/external/libunwind/src/ppc32/
H A DGregs.c31 tdep_access_reg (struct cursor *c, unw_regnum_t reg, unw_word_t *valp, argument
36 switch (reg)
62 if ((((unsigned) (reg - UNW_PPC32_F0)) <= 31))
65 loc = c->dwarf.loc[reg];
74 tdep_access_fpreg (struct cursor *c, unw_regnum_t reg, unw_fpreg_t *valp, argument
79 if ((unsigned) (reg - UNW_PPC32_F0) < 32)
81 loc = c->dwarf.loc[reg];
/external/libunwind/src/x86_64/
H A DGregs.c32 linux_scratch_loc (struct cursor *c, unw_regnum_t reg)
39 return DWARF_REG_LOC (&c->dwarf, reg);
50 return DWARF_REG_LOC (&c->dwarf, reg);
55 x86_64_scratch_loc (struct cursor *c, unw_regnum_t reg)
58 return linux_scratch_loc (c, reg);
60 return DWARF_REG_LOC (&c->dwarf, reg);
65 tdep_access_reg (struct cursor *c, unw_regnum_t reg, unw_word_t *valp, argument
72 switch (reg)
90 arg_num = reg - UNW_X86_64_RAX;
104 loc = c->dwarf.loc[(reg
134 tdep_access_fpreg(struct cursor *c, unw_regnum_t reg, unw_fpreg_t *valp, int write) argument
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/external/mesa3d/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir.cpp96 imm.reg.type = type;
221 memset(&reg, 0, sizeof(reg));
222 reg.size = 4;
227 reg.file = file;
228 reg.size = (file != FILE_PREDICATE) ? 4 : 1;
229 reg.data.id = -1;
244 reg.file = lval->reg.file;
245 reg
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/external/capstone/arch/Sparc/
H A DSparcInstPrinter.h15 void Sparc_addReg(MCInst *MI, int reg);
/external/libxaac/decoder/
H A Dixheaacd_adts_crc_check.c126 ia_bit_buf_struct *it_bit_buff_src, WORD32 reg) {
127 ptr_adts_crc_info->str_crc_reg_data[reg].active = 0;
128 ptr_adts_crc_info->str_crc_reg_data[reg].bit_buf_cnt =
129 ptr_adts_crc_info->str_crc_reg_data[reg].str_bit_buf.cnt_bits -
155 WORD32 reg; local
158 for (reg = 0; reg < ptr_adts_crc_info->no_reg; reg++) {
162 ptr_reg_data = &ptr_adts_crc_info->str_crc_reg_data[reg];
165 if (ptr_adts_crc_info->str_crc_reg_data[reg]
125 ixheaacd_adts_crc_end_reg(ia_adts_crc_info_struct *ptr_adts_crc_info, ia_bit_buf_struct *it_bit_buff_src, WORD32 reg) argument
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/external/mesa3d/src/gallium/drivers/freedreno/a2xx/
H A Dir-a2xx.c45 static void reg_update_stats(struct ir2_register *reg,
47 static uint32_t reg_fetch_src_swiz(struct ir2_register *reg, uint32_t n);
48 static uint32_t reg_fetch_dst_swiz(struct ir2_register *reg);
49 static uint32_t reg_alu_dst_swiz(struct ir2_register *reg);
50 static uint32_t reg_alu_src_swiz(struct ir2_register *reg);
282 int reg = 0; local
283 struct ir2_register *dst_reg = instr->regs[reg++];
284 struct ir2_register *src_reg = instr->regs[reg++];
365 int reg = 0; local
367 struct ir2_register *dst_reg = instr->regs[reg
494 struct ir2_register *reg = local
506 reg_update_stats(struct ir2_register *reg, struct ir2_shader_info *info, bool dest) argument
524 reg_fetch_src_swiz(struct ir2_register *reg, uint32_t n) argument
549 reg_fetch_dst_swiz(struct ir2_register *reg) argument
582 reg_alu_dst_swiz(struct ir2_register *reg) argument
609 reg_alu_src_swiz(struct ir2_register *reg) argument
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/external/syslinux/gpxe/src/drivers/net/
H A Detherfabric.c375 efab_dword_t reg; local
377 reg.opaque = falcon_mdio_read ( efab, mmd,
379 status = EFAB_DWORD_FIELD ( reg,
1163 #define FCN_REVISION_REG(efab, reg) \
1164 ( ( efab->pci_revision == FALCON_REV_B0 ) ? reg ## _B0 : reg ## _A1 )
1166 #define EFAB_SET_OWORD_FIELD_VER(efab, reg, field, val) \
1168 EFAB_SET_OWORD_FIELD ( reg, field ## _B0, val ); \
1170 EFAB_SET_OWORD_FIELD ( reg, field ## _A1, val );
1176 unsigned int reg ) {
1223 unsigned int reg = ( FCN_REVISION_REG ( efab, FCN_BUF_FULL_TBL_KER ) + local
1271 unsigned int reg = ( FCN_REVISION_REG ( efab, FCN_BUF_FULL_TBL_KER ) + local
1331 efab_dword_t reg; local
1403 efab_oword_t reg; local
1425 efab_oword_t reg; local
1515 efab_oword_t reg; local
1538 efab_oword_t reg; local
1600 efab_oword_t reg; local
1653 efab_oword_t reg; local
1725 efab_oword_t reg; local
1911 efab_dword_t reg; local
1936 efab_dword_t reg; local
2132 efab_dword_t reg; local
2153 efab_dword_t reg; local
2175 efab_dword_t reg; local
2195 efab_dword_t reg; local
2220 efab_dword_t reg; local
2263 efab_dword_t reg; local
2670 int rc, reg; local
2750 int rc, reg, i; local
2850 efab_dword_t reg; local
3379 efab_oword_t reg; local
3419 efab_oword_t reg; local
3508 efab_oword_t reg; local
3612 efab_dword_t reg; local
3640 efab_dword_t reg; local
3804 efab_dword_t reg; local
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/external/v8/src/crankshaft/
H A Dlithium-allocator-inl.h48 void LAllocator::SetLiveRangeAssignedRegister(LiveRange* range, int reg) { argument
50 assigned_double_registers_->Add(reg);
53 assigned_registers_->Add(reg);
55 range->set_assigned_register(reg, chunk()->zone());
/external/google-breakpad/src/common/
H A Ddwarf_cfi_to_module.h82 virtual void UnnamedRegister(size_t offset, int reg);
86 virtual void UndefinedNotSupported(size_t offset, const string &reg);
92 virtual void ExpressionsNotSupported(size_t offset, const string &reg);
143 virtual bool UndefinedRule(uint64 address, int reg);
144 virtual bool SameValueRule(uint64 address, int reg);
145 virtual bool OffsetRule(uint64 address, int reg,
147 virtual bool ValOffsetRule(uint64 address, int reg,
149 virtual bool RegisterRule(uint64 address, int reg, int base_register);
150 virtual bool ExpressionRule(uint64 address, int reg,
152 virtual bool ValExpressionRule(uint64 address, int reg,
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