/external/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 255 AMDGPU::OpName::src2 266 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel}, 319 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
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H A D | SIInstrInfo.cpp | 1241 MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2); 1273 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)); 1312 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)); 1318 // These come before src2. 1435 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2); 1654 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2); 1766 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2"; 2135 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)
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/external/valgrind/VEX/priv/ |
H A D | host_s390_defs.h | 443 s390_opnd_RMI src2; member in struct:__anon28559::__anon28560::__anon28573
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H A D | host_ppc_defs.h | 956 HReg src2; member in struct:__anon28460::__anon28461::__anon28515 1159 HReg src1, HReg src2 );
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/external/wpa_supplicant_8/hostapd/src/utils/ |
H A D | common.h | 508 const u8 *src2, size_t src2_len);
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/external/wpa_supplicant_8/src/utils/ |
H A D | common.h | 508 const u8 *src2, size_t src2_len);
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/external/wpa_supplicant_8/wpa_supplicant/src/utils/ |
H A D | common.h | 508 const u8 *src2, size_t src2_len);
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/external/swiftshader/src/OpenGL/compiler/ |
H A D | OutputASM.cpp | 2049 Instruction *OutputASM::emit(sw::Shader::Opcode op, TIntermTyped *dst, TIntermNode *src0, TIntermNode *src1, TIntermNode *src2, TIntermNode *src3, TIntermNode *src4) argument 2051 return emit(op, dst, 0, src0, 0, src1, 0, src2, 0, src3, 0, src4, 0); 2055 TIntermNode *src2, int index2, TIntermNode *src3, int index3, TIntermNode *src4, int index4) 2072 source(instruction->src[2], src2, index2); 2135 void OutputASM::emitBinary(sw::Shader::Opcode op, TIntermTyped *dst, TIntermNode *src0, TIntermNode *src1, TIntermNode *src2) argument 2139 emit(op, dst, index, src0, index, src1, index, src2, index); 2054 emit(sw::Shader::Opcode op, TIntermTyped *dst, int dstIndex, TIntermNode *src0, int index0, TIntermNode *src1, int index1, TIntermNode *src2, int index2, TIntermNode *src3, int index3, TIntermNode *src4, int index4) argument
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/external/mesa3d/src/amd/common/ |
H A D | ac_nir_to_llvm.c | 766 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2) 771 to_float(ctx, src2), 777 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2) 781 return LLVMBuildSelect(ctx->builder, v, src1, src2, ""); 966 LLVMValueRef src2, LLVMValueRef src3) 976 src2, ""); 977 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, ""); 764 emit_intrin_3f_param(struct nir_to_llvm_context *ctx, const char *intrin, LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2) argument 776 emit_bcsel(struct nir_to_llvm_context *ctx, LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2) argument 964 emit_bitfield_insert(struct nir_to_llvm_context *ctx, LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2, LLVMValueRef src3) argument
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/external/v8/src/s390/ |
H A D | simulator-s390.cc | 2385 // Test src1 and src2 have opposite sign, 2390 #define CheckOverflowForIntAdd(src1, src2, type) \ 2391 OverflowFromSigned<type>(src1 + src2, src1, src2, true); 2393 #define CheckOverflowForIntSub(src1, src2, type) \ 2394 OverflowFromSigned<type>(src1 - src2, src1, src2, false); 2397 #define CheckOverflowForUIntAdd(src1, src2) \ 2398 ((src1) + (src2) < (src1) || (src1) + (src2) < (src [all...] |
/external/mesa3d/src/mesa/state_tracker/ |
H A D | st_glsl_to_tgsi.cpp | 502 st_src_reg src2 = undef_src, 509 st_src_reg src2 = undef_src, 647 st_src_reg src2, st_src_reg src3) 663 num_reladdr += src2.reladdr != NULL || src2.reladdr2 != NULL; 667 reladdr_to_temp(ir, &src2, &num_reladdr); 693 inst->src[2] = src2; 878 st_src_reg src2, st_src_reg src3) 880 return emit_asm(ir, op, dst, undef_dst, src0, src1, src2, src3); 644 emit_asm(ir_instruction *ir, unsigned op, st_dst_reg dst, st_dst_reg dst1, st_src_reg src0, st_src_reg src1, st_src_reg src2, st_src_reg src3) argument 875 emit_asm(ir_instruction *ir, unsigned op, st_dst_reg dst, st_src_reg src0, st_src_reg src1, st_src_reg src2, st_src_reg src3) argument
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/external/python/cpython2/Mac/Modules/qd/ |
H A D | _Qdmodule.c | 2214 Rect src2; local 2221 PyMac_GetRect, &src2)) 2224 &src2, 2236 Rect src2; local 2243 PyMac_GetRect, &src2)) 2246 &src2, 6127 Rect src2; local 6134 PyMac_GetRect, &src2)) 6137 &src2, 6621 PyDoc_STR("(Rect src1, Rect src2) [all...] |
/external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
H A D | nv50_ir_peephole.cpp | 384 ImmediateValue src0, src1, src2; local 389 i->src(2).getImmediate(src2)) 390 expr(i, src0, src1, src2); 401 if (i->srcExists(2) && i->src(2).getImmediate(src2)) 402 opnd3(i, src2);
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/external/libdrm/intel/ |
H A D | intel_decode.c | 887 char dst[100], src0[100], src1[100], src2[100]; local 892 i915_get_instruction_src2(ctx->data, i, src2); 895 op_name, dst, src0, src1, src2);
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_vec4_generator.cpp | 663 struct brw_reg src2) 672 brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0), 676 suboffset(vec1(src2), 0)); 659 generate_gs_ff_sync_set_primitives(struct brw_codegen *p, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1, struct brw_reg src2) argument
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/external/swiftshader/src/Shader/ |
H A D | PixelProgram.cpp | 113 const Src &src2 = instruction->src[2]; local 147 if(src2.type != Shader::PARAMETER_VOID) s2 = fetchRegister(src2);
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H A D | VertexProgram.cpp | 131 Src src2 = instruction->src[2]; local 149 if(src2.type != Shader::PARAMETER_VOID) s2 = fetchRegister(src2);
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/external/libvpx/libvpx/third_party/x86inc/ |
H A D | x86inc.asm | 1258 ; 3-operand AVX instructions with a memory arg can only have it in src2, 1599 ; Macros for consolidating FMA3 and FMA4 using 4-operand (dst, src1, src2, src3) syntax. 1601 ; Either src2 or src3 can be a memory operand.
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/external/mesa3d/src/compiler/nir/ |
H A D | nir.h | 806 unsigned src1, unsigned src2); 2177 bool nir_srcs_equal(nir_src src1, nir_src src2);
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/external/opencv/cv/src/ |
H A D | cvlkpyramid.cpp | 238 const float* src2 = src + src_step; local 243 float t0 = (src3[x] + src[x])*smooth_k[0] + src2[x]*smooth_k[1];
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/external/skia/src/core/ |
H A D | SkGeometry.cpp | 721 const SkScalar src2[] = { 0, 1 }; 733 { TEST_COLLAPS_ENTRY(src2), 2 },
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/external/skqp/src/core/ |
H A D | SkGeometry.cpp | 721 const SkScalar src2[] = { 0, 1 }; 733 { TEST_COLLAPS_ENTRY(src2), 2 },
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/external/v8/src/arm64/ |
H A D | macro-assembler-arm64-inl.h | 1351 void MacroAssembler::SmiTagAndPush(Register src1, Register src2) { argument 1355 Push(src1.W(), wzr, src2.W(), wzr);
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/external/mesa3d/src/compiler/glsl/ |
H A D | glsl_to_nir.cpp | 82 nir_ssa_def *src2); 84 nir_ssa_def *src2, nir_ssa_def *src3);
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/external/mesa3d/src/gallium/drivers/svga/ |
H A D | svga_tgsi_vgpu10.c | 3106 const struct tgsi_full_src_register *src2, 3113 emit_src_register(emit, src2); 3122 const struct tgsi_full_src_register *src2, 3130 emit_src_register(emit, src2); 3542 /* dst.x = (src0.x < 0) ? src1.x : src2.x 3543 * dst.y = (src0.y < 0) ? src1.y : src2.y 3544 * dst.z = (src0.z < 0) ? src1.z : src2.z 3545 * dst.w = (src0.w < 0) ? src1.w : src2.w 3549 * MOVC dst, tmp, src1, src2 3575 /* dst.x = src0.x * src1.x + src0.y * src1.y + src2 3102 emit_instruction_op2(struct svga_shader_emitter_v10 *emit, unsigned opcode, const struct tgsi_full_dst_register *dst, const struct tgsi_full_src_register *src1, const struct tgsi_full_src_register *src2, boolean saturate) argument 3118 emit_instruction_op3(struct svga_shader_emitter_v10 *emit, unsigned opcode, const struct tgsi_full_dst_register *dst, const struct tgsi_full_src_register *src1, const struct tgsi_full_src_register *src2, const struct tgsi_full_src_register *src3, boolean saturate) argument [all...] |