Searched refs:IoBase (Results 1 - 25 of 28) sorted by relevance

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/device/linaro/bootloader/edk2/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/
H A DPciHostResource.h36 UINTN IoBase; member in struct:__anon9949
H A DPciHostBridge.c164 PrivateData->Aperture.IoBase = PcdGet16 (PcdPciHostBridgeIoBase);
411 if (RootBridgeInstance->Aperture.IoBase < RootBridgeInstance->Aperture.IoLimit) {
418 BaseAddress = RootBridgeInstance->Aperture.IoBase;
/device/linaro/bootloader/edk2/ArmVirtPkg/Library/FdtPciHostBridgeLib/
H A DFdtPciHostBridgeLib.c88 OUT UINT64 *IoBase,
114 *IoBase = 0;
209 *IoBase = SwapBytes64 (Record->ChildBase);
211 IoTranslation = SwapBytes64 (Record->CpuBase) - *IoBase;
267 __FUNCTION__, ConfigBase, ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize,
289 UINT64 IoBase, IoSize; local
302 Status = ProcessPciHost (&IoBase, &IoSize, &Mmio32Base, &Mmio32Size,
328 mRootBridge.Io.Base = IoBase;
329 mRootBridge.Io.Limit = IoBase + IoSize - 1;
87 ProcessPciHost( OUT UINT64 *IoBase, OUT UINT64 *IoSize, OUT UINT64 *Mmio32Base, OUT UINT64 *Mmio32Size, OUT UINT64 *Mmio64Base, OUT UINT64 *Mmio64Size, OUT UINT32 *BusMin, OUT UINT32 *BusMax ) argument
/device/linaro/bootloader/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/
H A DFdtPciPcdProducerLib.c58 UINT64 IoBase; local
78 IoBase = SwapBytes64 (Record->ChildBase);
79 *IoTranslation = SwapBytes64 (Record->CpuBase) - IoBase;
/device/linaro/bootloader/edk2/CorebootModulePkg/Library/BaseSerialPortLib16550/
H A DBaseSerialPortLib16550.c197 UINT32 IoBase; local
274 IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase));
275 if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
276 IoBase = IoBase >> 4;
278 IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBaseUpper16)) << 4) | (IoBase >> 4);
284 if (IoLimit < IoBase) {
291 if (IoBase < ParentIoBas
[all...]
/device/linaro/bootloader/edk2/MdeModulePkg/Library/BaseSerialPortLib16550/
H A DBaseSerialPortLib16550.c197 UINT32 IoBase; local
274 IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase));
275 if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
276 IoBase = IoBase >> 4;
278 IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBaseUpper16)) << 4) | (IoBase >> 4);
284 if (IoLimit < IoBase) {
291 if (IoBase < ParentIoBas
[all...]
/device/linaro/bootloader/edk2/DuetPkg/PciRootBridgeNoEnumerationDxe/
H A DPcatPciRootBridge.c105 PrivateData->IoBase = 0xffffffff;
251 Value = PciConfigurationHeader.Bridge.IoBase & 0x0f;
252 Base = ((UINT32)PciConfigurationHeader.Bridge.IoBase & 0xf0) << 8;
259 if (PrivateData->IoBase > Base) {
260 PrivateData->IoBase = Base;
434 PrivateData->IoBase = 0;
572 if (PrivateData->IoLimit >= PrivateData->IoBase) {
651 if (PrivateData->IoLimit >= PrivateData->IoBase) {
656 Configuration->AddrRangeMin = PrivateData->IoBase;
866 if (PrivateData->IoBase > Bas
[all...]
H A DPcatPciRootBridge.h66 UINT64 IoBase; // Offsets host to bus io addr. member in struct:__anon4108
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformInitPei/
H A DMemoryCallback.c150 UINT32 IoBase;
216 IoBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_IO_BASE ) & B_PCH_LPC_IO_BASE_BAR;
220 IoBase,
223 DEBUG ((EFI_D_INFO, "IoBase : 0x%x\n", IoBase));
141 UINT32 IoBase; local
H A DPchInitPeim.c619 UINT32 IoBase;
655 PchPlatformPolicyPpi->IoBase = IO_BASE_ADDRESS;
712 IoBase = MmioRead32 (MmPciAddress (0,
718 MmioAnd32 ((UINTN) (IoBase + 0x270), (UINT32) (~0x07));
610 UINT32 IoBase; local
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/PciBusDxe/
H A DPciEnumerator.h270 @param IoBase Output of I/O resource base address.
280 OUT UINT64 *IoBase,
320 @param IoBase Output for base address of I/O type resource.
333 OUT UINT64 *IoBase,
H A DPciEnumerator.c1329 @param IoBase Output of I/O resource base address.
1339 OUT UINT64 *IoBase,
1352 *IoBase = 0xFFFFFFFFFFFFFFFFULL;
1399 *IoBase = Ptr->AddrRangeMin;
1497 UINT64 IoBase; local
1563 &IoBase,
1578 IoBase,
1633 @param IoBase Output for base address of I/O type resource.
1646 OUT UINT64 *IoBase,
1657 *IoBase
1337 GetResourceBase( IN VOID *Config, OUT UINT64 *IoBase, OUT UINT64 *Mem32Base, OUT UINT64 *PMem32Base, OUT UINT64 *Mem64Base, OUT UINT64 *PMem64Base ) argument
1644 GetResourceBaseFromBridge( IN PCI_IO_DEVICE *Bridge, OUT UINT64 *IoBase, OUT UINT64 *Mem32Base, OUT UINT64 *PMem32Base, OUT UINT64 *Mem64Base, OUT UINT64 *PMem64Base ) argument
[all...]
H A DPciLib.c370 UINT64 IoBase; local
787 &IoBase,
819 IoBase,
855 IoBridge ->PciDev->PciBar[IoBridge ->Bar].BaseAddress = IoBase;
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/
H A DPchPlatformPolicy.h151 UINT32 IoBase; // IO Base Address. member in struct:_PCH_PLATFORM_POLICY_PPI
/device/linaro/bootloader/edk2/DuetPkg/PciBusNoEnumerationDxe/
H A DPciDeviceSupport.c494 if ((((PciData.Bridge.IoBase & 0xF) == 0) &&
495 (PciData.Bridge.IoBase != 0 || PciData.Bridge.IoLimit != 0)) ||
496 (((PciData.Bridge.IoBase & 0xF) == 1) &&
497 ((PciData.Bridge.IoBase & 0xF0) != 0 || (PciData.Bridge.IoLimit & 0xF0) != 0 || PciData.Bridge.IoBaseUpper16 != 0 || PciData.Bridge.IoLimitUpper16 != 0))) {
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformPei/
H A DPlatform.c224 UINT32 IoBase = 0;
233 IoBase = MmioRead32 (PciD31F0RegBase + R_PCH_LPC_IO_BASE) & B_PCH_LPC_IO_BASE_BAR;
235 MmioConf0 = IoBase + SSUSOffset + PConf0Offset;
236 MmioPadval = IoBase + SSUSOffset + PValueOffset;
215 UINT32 IoBase = 0; local
/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/
H A DPciRootBridgeIo.c687 void SetAtuIoRW(UINT64 RbPciBase,UINT64 IoBase,UINT64 CpuIoRegionLimit, UINT64 CpuIoRegionBase, UINT32 Index) argument
696 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(IoBase));
697 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(IoBase) >> 32));
736 SetAtuIoRW (Private->RbPciBar, Private->IoBase, Private->IoLimit, Private->CpuIoRegionBase, 3);
796 PrivateData->IoBase = ResAppeture->IoBase;
971 Base = PrivateData->IoBase;
1166 Address -= PrivateData->IoBase;
H A DPciHostBridge.h468 UINT64 IoBase; member in struct:__anon1355
/device/linaro/bootloader/edk2/OvmfPkg/Library/PciHostBridgeLib/
H A DXenSupport.c279 Value = Pci.Bridge.IoBase & 0x0f;
280 Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;
/device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/
H A DLan91xDxe.c72 UINTN IoBase; // I/O Base Address member in struct:_LAN91X_DRIVER
223 MmioWrite16 (LanDriver->IoBase + LAN91X_BANK_OFFSET, Bank);
243 return MmioRead16 (LanDriver->IoBase + Offset);
262 return MmioWrite16 (LanDriver->IoBase + Offset, Value);
280 return MmioRead8 (LanDriver->IoBase + Offset);
299 return MmioWrite8 (LanDriver->IoBase + Offset, Value);
451 Value = MmioRead16 (LanDriver->IoBase + LAN91X_BANK_OFFSET);
900 Bank = MmioRead16 (LanDriver->IoBase + LAN91X_BANK_OFFSET);
910 Bank = MmioRead16 (LanDriver->IoBase + LAN91X_BANK_OFFSET);
2133 LanDriver->IoBase
[all...]
/device/linaro/bootloader/edk2/CorebootPayloadPkg/Library/PciHostBridgeLib/
H A DPciHostBridgeSupport.c405 Value = Pci.Bridge.IoBase & 0x0f;
406 Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;
/device/linaro/bootloader/edk2/DuetPkg/PciRootBridgeNoEnumerationDxe/Ipf/
H A DPcatIo.c80 if ( Address < PrivateData->IoBase || Address > PrivateData->IoLimit ) {
183 if ( Address < PrivateData->IoBase || Address > PrivateData->IoLimit ) {
/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Include/Library/
H A DPlatformPciLib.h198 UINT64 IoBase; member in struct:__anon1432
/device/linaro/bootloader/edk2/BaseTools/Source/C/Include/IndustryStandard/
H A Dpci22.h71 UINT8 IoBase; member in struct:__anon3908
/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/
H A Dpci22.h78 UINT8 IoBase; member in struct:__anon5043

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