| /external/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64ExternalSymbolizer.cpp | 107 MI.getOpcode() == AArch64::ADR) {
116 } else if (MI.getOpcode() == AArch64::ADR) {
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| /external/vixl/src/aarch64/ |
| H A D | instructions-aarch64.cc | 293 // ADR and ADRP.
299 VIXL_ASSERT(Mask(PCRelAddressingMask) == ADR);
339 if ((Mask(PCRelAddressingMask) == ADR)) {
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| H A D | constants-aarch64.h | 401 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break;
461 ADR = PCRelAddressingFixed | 0x00000000, enumerator in enum:vixl::aarch64::PCRelAddressingOp
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| H A D | disasm-aarch64.cc | 581 case ADR:
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| H A D | simulator-aarch64.cc | 991 VIXL_ASSERT((instr->Mask(PCRelAddressingMask) == ADR) ||
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| /external/syslinux/gpxe/src/include/gpxe/efi/Protocol/ |
| H A D | DevicePath.h | 156 UINT32 ADR; member in struct:__anon24994
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| /external/v8/src/arm64/ |
| H A D | instructions-arm64.h | 197 return Mask(PCRelAddressingMask) == ADR;
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| H A D | disasm-arm64.cc | 521 case ADR: Format(instr, "adr", "'Xd, 'AddrPCRelByte"); break;
1594 // Only ADR (AddrPCRelByte) is supported.
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| H A D | constants-arm64.h | 402 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break;
421 ADR = PCRelAddressingFixed | 0x00000000, enumerator in enum:v8::internal::PCRelAddressingOp
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| H A D | assembler-arm64.cc | 801 // could be useful for ADR, for example.)
842 // ADR instructions are not handled by veneers.
1084 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd));
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| H A D | simulator-arm64.cc | 1333 case ADR:
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| /external/llvm/lib/Transforms/Scalar/ |
| H A D | LoopRerollPass.cpp | 967 const auto *ADR = dyn_cast<SCEVAddRecExpr>(SE->getSCEV(V.BaseInst)); local
968 if (!ADR)
982 const SCEV *StepSCEV = SE->getMinusSCEV(SE->getSCEV(V.Roots[0]), ADR);
984 if (ADR->getStepRecurrence(*SE) != SE->getMulExpr(StepSCEV, ScaleSCEV)) {
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| /external/tremolo/Tremolo/ |
| H A D | dpen.s | 63 ADR r14,dpen_read_return
460 ADR r6,.Lcrc_lookup
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| H A D | mdctARM.s | 1003 ADR r6, bitrev
1033 ADR r7, .Lsincos_lookup @ sincos_lookup0 +
1127 ADR r7, .Lsincos_lookup @ sincos_lookup0 +
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| H A D | mdctLARM.s | 989 ADR r6, bitrev
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCCodeEmitter.cpp | 66 /// getAdrLabelOpValue - Return encoding info for 21-bit immediate ADR label
215 /// getAdrLabelOpValue - Return encoding info for 21-bit immediate ADR label
229 MCFixupKind Kind = MI.getOpcode() == AArch64::ADR
349 assert(MO.isExpr() && "Unexpected ADR target type!");
371 assert(MO.isExpr() && "Unexpected ADR target type!");
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 1310 : ARM::ADR))
1326 : ARM::ADR))
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| /external/llvm/test/MC/ARM/ |
| H A D | basic-thumb-instructions.s | 86 @ ADR
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| H A D | v8_IT_manual.s | 501 @ ADR, encoding T1
505 @ ADR, encoding T2 (32-bit)
509 @ ADR, encoding T3 (32-bit)
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| H A D | basic-thumb-instructions.s | 81 @ ADR
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| H A D | basic-arm-instructions.s | 126 @ ADR
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 1215 : ARM::ADR));
1229 : ARM::ADR));
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| /external/capstone/arch/ARM/ |
| H A D | ARMGenAsmWriter.inc | 52 18806U, // ADR
2845 8U, // ADR
6091 // ADR, CLZ, CMNri, CMNzrr, CMPri, CMPrr, FCONSTD, FCONSTS, FLDMXDB_UPD, ...
6226 // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ADR, ANDri, ANDrr, ANDrsi,...
6708 // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ADR, ANDri, ANDrr, ANDrsi,...
7066 // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ADR, ANDri, ANDrr, ANDrsi,...
7226 // ADR, t2ADR
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| /external/v8/src/s390/ |
| H A D | constants-s390.h | 1569 V(adr, ADR, 0x2A) /* type = RR ADD NORMALIZED (long HFP) */ \
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| /external/capstone/arch/AArch64/ |
| H A D | AArch64GenAsmWriter.inc | 96 553920403U, // ADR
2488 0U, // ADR
5929 // ABSv1i64, ADR, CLSWr, CLSXr, CLZWr, CLZXr, DUPv16i8gpr, DUPv2i32gpr, D...
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