Searched refs:CCR (Results 1 - 10 of 10) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp248 ARMCC::CondCodes CCVal, SDValue CCR,
251 ARMCC::CondCodes CCVal, SDValue CCR,
254 ARMCC::CondCodes CCVal, SDValue CCR,
257 ARMCC::CondCodes CCVal, SDValue CCR,
2105 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2124 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
2132 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2138 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp2, CC, CCR, InFlag };
2144 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
2152 ARMCC::CondCodes CCVal, SDValue CCR, SDValu
2104 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) argument
2131 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) argument
2151 SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) argument
2182 SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) argument
2219 SDValue CCR = N->getOperand(3); local
[all...]
H A DARMISelLowering.cpp2772 SDValue CCR = Cond.getOperand(3); local
2775 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2796 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); local
2798 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2806 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); local
2808 ARMcc, CCR, Cmp);
2814 Result, TrueVal, ARMcc2, CCR, Cmp2);
2916 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); local
2918 Chain, Dest, ARMcc, CCR, Cmp);
2946 SDValue CCR local
2966 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); local
3282 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); local
3316 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); local
[all...]
/external/capstone/arch/AArch64/
H A DAArch64GenRegisterInfo.inc1134 // CCR Register Class...
1135 static MCPhysReg CCR[] = {
1139 // CCR Bit set.
1502 { "CCR", CCR, CCRBits, 1, sizeof(CCRBits), AArch64_CCRRegClassID, 4, 4, -1, 0 },
/external/capstone/arch/Mips/
H A DMipsGenRegisterInfo.inc1006 // CCR Register Class...
1007 static MCPhysReg CCR[] = {
1011 // CCR Bit set.
1478 { "CCR", CCR, CCRBits, 32, sizeof(CCRBits), Mips_CCRRegClassID, 4, 4, 1, 0 },
/external/capstone/arch/X86/
H A DX86GenRegisterInfo.inc1017 // CCR Register Class...
1018 static MCPhysReg CCR[] = {
1022 // CCR Bit set.
1472 { CAPSTONE_REGISTER_CLASS("CCR"), CCR, CCRBits, 1, sizeof(CCRBits), X86_CCRRegClassID, 4, 4, -1, 0 },
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp3564 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); local
3572 ARMcc, CCR, OverflowCmp);
3595 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); local
3598 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
3630 SDValue CCR = Cond.getOperand(3); local
3633 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
3698 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
3712 ARMcc, CCR, Cmp);
3714 ARMcc, CCR, duplicateCmp(Cmp, DAG));
3718 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
3697 getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal, SDValue ARMcc, SDValue CCR, SDValue Cmp, SelectionDAG &DAG) const argument
3901 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); local
3927 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); local
4039 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); local
4083 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); local
4102 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); local
4540 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); local
4574 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); local
5027 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); local
[all...]
H A DARMISelLowering.h657 SDValue ARMcc, SDValue CCR, SDValue Cmp,
/external/libunwind/src/ptrace/
H A D_UPT_reg_offset.c424 [UNW_PPC32_CCR] = UNW_PPC_PT(CCR)
/external/capstone/arch/ARM/
H A DARMGenRegisterInfo.inc1298 // CCR Register Class...
1299 static uint16_t CCR[] = {
1303 // CCR Bit set.
2191 { "CCR", CCR, CCRBits, 1, sizeof(CCRBits), ARM_CCRRegClassID, 4, 4, -1, 0 },
/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86GenRegisterInfo.inc1118 // CCR Register Class...
1119 static const unsigned CCR[] = {
1123 // CCR Bit set.
1170 MCRegisterClass(X86::CCRRegClassID, "CCR", 4, 4, -1, 0, CCR, CCR + 1, CCRBits, sizeof(CCRBits)),
3114 // CCR Super-register Classes...
5005 { // CCR

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