/external/pcre/dist2/src/sljit/ |
H A D | sljitNativeSPARC_32.c | 30 return push_inst(compiler, OR | D(dst) | S1(0) | IMM(imm), DR(dst)); 32 FAIL_IF(push_inst(compiler, SETHI | D(dst) | ((imm >> 10) & 0x3fffff), DR(dst))); 33 return (imm & 0x3ff) ? push_inst(compiler, OR | D(dst) | S1(dst) | IMM_ARG | (imm & 0x3ff), DR(dst)) : SLJIT_SUCCESS; 50 return push_inst(compiler, OR | D(dst) | S1(0) | S2(src2), DR(dst)); 58 return push_inst(compiler, AND | D(dst) | S1(src2) | IMM(0xff), DR(dst)); 59 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src2) | IMM(24), DR(dst))); 60 return push_inst(compiler, SRA | D(dst) | S1(dst) | IMM(24), DR(dst)); 70 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src2) | IMM(16), DR(dst))); 71 return push_inst(compiler, (op == SLJIT_MOV_S16 ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst)); 79 return push_inst(compiler, XNOR | (flags & SET_FLAGS) | D(dst) | S1(0) | S2(src2), DR(ds [all...] |
H A D | sljitNativeMIPS_64.c | 129 FAIL_IF(push_inst(compiler, op_imm | S(src1) | T(dst) | IMM(src2), DR(dst))); \ 135 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | D(dst), DR(dst))); \ 150 FAIL_IF(push_inst(compiler, ins | T(src1) | D(dst) | SH_IMM(src2), DR(dst))); \ 157 FAIL_IF(push_inst(compiler, ins | S(src2) | T(src1) | D(dst), DR(dst))); \ 170 return push_inst(compiler, SELECT_OP(DADDU, ADDU) | S(src2) | TA(0) | D(dst), DR(dst)); 178 FAIL_IF(push_inst(compiler, DSLL32 | T(src2) | D(dst) | SH_IMM(24), DR(dst))); 179 return push_inst(compiler, DSRA32 | T(dst) | D(dst) | SH_IMM(24), DR(dst)); 181 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xff), DR(dst)); 192 FAIL_IF(push_inst(compiler, DSLL32 | T(src2) | D(dst) | SH_IMM(16), DR(dst))); 193 return push_inst(compiler, DSRA32 | T(dst) | D(dst) | SH_IMM(16), DR(ds [all...] |
H A D | sljitNativeMIPS_32.c | 46 FAIL_IF(push_inst(compiler, op_imm | S(src1) | T(dst) | IMM(src2), DR(dst))); \ 52 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | D(dst), DR(dst))); \ 60 FAIL_IF(push_inst(compiler, op_imm | T(src1) | D(dst) | SH_IMM(src2), DR(dst))); \ 66 FAIL_IF(push_inst(compiler, op_v | S(src2) | T(src1) | D(dst), DR(dst))); \ 79 return push_inst(compiler, ADDU | S(src2) | TA(0) | D(dst), DR(dst)); 88 return push_inst(compiler, SEB | T(src2) | D(dst), DR(dst)); 90 FAIL_IF(push_inst(compiler, SLL | T(src2) | D(dst) | SH_IMM(24), DR(dst))); 91 return push_inst(compiler, SRA | T(dst) | D(dst) | SH_IMM(24), DR(dst)); 94 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xff), DR(dst)); 106 return push_inst(compiler, SEH | T(src2) | D(dst), DR(ds [all...] |
H A D | sljitNativeMIPS_common.c | 92 #define DR(dr) (reg_map[dr]) macro 562 FAIL_IF(push_inst(compiler, ADDIU_W | S(SLJIT_SP) | T(SLJIT_SP) | IMM(-local_size), DR(SLJIT_SP))); 566 FAIL_IF(load_immediate(compiler, DR(TMP_REG1), local_size)); 567 FAIL_IF(push_inst(compiler, ADDU_W | S(SLJIT_SP) | TA(0) | D(TMP_REG2), DR(TMP_REG2))); 568 FAIL_IF(push_inst(compiler, SUBU_W | S(SLJIT_SP) | T(TMP_REG1) | D(SLJIT_SP), DR(SLJIT_SP))); 588 FAIL_IF(push_inst(compiler, ADDU_W | SA(4) | TA(0) | D(SLJIT_S0), DR(SLJIT_S0))); 590 FAIL_IF(push_inst(compiler, ADDU_W | SA(5) | TA(0) | D(SLJIT_S1), DR(SLJIT_S1))); 592 FAIL_IF(push_inst(compiler, ADDU_W | SA(6) | TA(0) | D(SLJIT_S2), DR(SLJIT_S2))); 628 FAIL_IF(load_immediate(compiler, DR(TMP_REG1), local_size)); 629 FAIL_IF(push_inst(compiler, ADDU_W | S(SLJIT_SP) | T(TMP_REG1) | D(TMP_REG1), DR(TMP_REG [all...] |
H A D | sljitNativeSPARC_common.c | 116 #define DR(dr) (reg_map[dr]) macro 526 ((flags & MEM_MASK) <= GPR_REG && (flags & LOAD_DATA)) ? DR(reg) : MOVABLE_INS)); 585 FAIL_IF(push_inst(compiler, SLL_W | D(arg2) | S1(OFFS_REG(arg)) | IMM_ARG | argw, DR(arg2))); 592 FAIL_IF(push_inst(compiler, ADD | D(TMP_REG3) | S1(TMP_REG3) | IMM(argw - compiler->cache_argw), DR(TMP_REG3))); 611 delay_slot = ((flags & MEM_MASK) <= GPR_REG && (flags & LOAD_DATA)) ? DR(reg) : MOVABLE_INS; 617 return push_inst(compiler, ADD | D(base) | S1(base) | S2(arg2), DR(base)); 779 FAIL_IF(push_inst(compiler, (op == SLJIT_LMUL_UW ? UMUL : SMUL) | D(SLJIT_R0) | S1(SLJIT_R0) | S2(SLJIT_R1), DR(SLJIT_R0))); 780 return push_inst(compiler, RDY | D(SLJIT_R1), DR(SLJIT_R1)); 793 FAIL_IF(push_inst(compiler, SRA | D(TMP_REG1) | S1(SLJIT_R0) | IMM(31), DR(TMP_REG1))); 797 FAIL_IF(push_inst(compiler, OR | D(TMP_REG2) | S1(0) | S2(SLJIT_R0), DR(TMP_REG [all...] |
/external/clang/lib/StaticAnalyzer/Core/ |
H A D | CheckerHelpers.cpp | 35 const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(S); local 37 if (DR && isa<EnumConstantDecl>(DR->getDecl())) 49 const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(S); local 51 if (DR) 52 if (const VarDecl *VD = dyn_cast<VarDecl>(DR->getDecl()))
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H A D | BugReporterVisitors.cpp | 321 if (const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(RetE)) 322 if (const DeclaratorDecl *DD = dyn_cast<DeclaratorDecl>(DR->getDecl())) 888 if (const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(E)) { 889 if (const VarDecl *VD = dyn_cast<VarDecl>(DR->getDecl())) { 1175 if (const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(Head)) { 1176 if (const VarDecl *VD = dyn_cast<VarDecl>(DR->getDecl())) { 1332 if (const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(Ex)) { 1333 const bool quotes = isa<VarDecl>(DR->getDecl()); 1338 if (const MemRegion *R = state->getLValue(cast<VarDecl>(DR->getDecl()), 1350 Out << DR 1510 VisitTrueTest(const Expr *Cond, const DeclRefExpr *DR, const bool tookTrue, BugReporterContext &BRC, BugReport &report, const ExplodedNode *N) argument [all...] |
/external/clang/lib/StaticAnalyzer/Checkers/ |
H A D | DeadStoresChecker.cpp | 54 bool VisitDeclRefExpr(DeclRefExpr *DR) { argument 56 if (const VarDecl *D = dyn_cast<VarDecl>(DR->getDecl())) 229 void CheckDeclRef(const DeclRefExpr *DR, const Expr *Val, DeadStoreKind dsk, argument 231 if (const VarDecl *VD = dyn_cast<VarDecl>(DR->getDecl())) 232 CheckVarDecl(VD, DR, Val, dsk, Live); 245 const DeclRefExpr *DR; local 247 if ((DR = dyn_cast<DeclRefExpr>(BRHS->getLHS()->IgnoreParenCasts()))) 248 if (DR->getDecl() == VD) 251 if ((DR = dyn_cast<DeclRefExpr>(BRHS->getRHS()->IgnoreParenCasts()))) 252 if (DR [all...] |
H A D | MallocOverflowSecurityChecker.cpp | 144 static const Decl *getDecl(const DeclRefExpr *DR) { return DR->getDecl(); } argument 150 void Erase(const T1 *DR, argument 152 auto P = [DR, Pred](const MallocOverflowCheck &Check) { 154 return getDecl(CheckDR) == getDecl(DR) && Pred(Check); 164 if (const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(E)) 165 Erase<DeclRefExpr>(DR, PredTrue); 218 if (const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(E)) 219 Erase<DeclRefExpr>(DR, pred);
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H A D | DereferenceChecker.cpp | 64 const DeclRefExpr *DR = cast<DeclRefExpr>(Ex); local 65 if (const VarDecl *VD = dyn_cast<VarDecl>(DR->getDecl())) { 68 Ranges.push_back(DR->getSourceRange());
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H A D | ObjCSelfInitChecker.cpp | 419 if (const DeclRegion *DR = dyn_cast<DeclRegion>(MRV.stripCasts())) 420 return (DR->getDecl() == analCtx->getSelfDecl());
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/external/clang/lib/Analysis/ |
H A D | LiveVariables.cpp | 208 void VisitDeclRefExpr(DeclRefExpr *DR); 340 if (DeclRefExpr *DR = dyn_cast<DeclRefExpr>(LHS)) 341 if (const VarDecl *VD = dyn_cast<VarDecl>(DR->getDecl())) { 352 observer->observerKill(DR); 366 void TransferFunctions::VisitDeclRefExpr(DeclRefExpr *DR) { argument 367 if (const VarDecl *D = dyn_cast<VarDecl>(DR->getDecl())) 368 if (!isAlwaysAlive(D) && LV.inAssignment.find(DR) == LV.inAssignment.end()) 382 DeclRefExpr *DR = nullptr; local 389 else if ((DR = dyn_cast<DeclRefExpr>(cast<Expr>(element)->IgnoreParens()))) { 390 VD = cast<VarDecl>(DR [all...] |
H A D | PseudoConstantAnalysis.cpp | 68 if (const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(E)) 69 return DR->getDecl(); 199 const DeclRefExpr *DR = cast<DeclRefExpr>(Head); local 200 if (const VarDecl *VD = dyn_cast<VarDecl>(DR->getDecl())) {
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H A D | BodyFarm.cpp | 110 DeclRefExpr *DR = local 119 return DR; 205 DeclRefExpr *DR = M.makeDeclRefExpr(Block); local 206 ImplicitCastExpr *ICE = M.makeLvalueToRvalue(DR, Ty); 267 DeclRefExpr *DR = M.makeDeclRefExpr(PV); local 268 ImplicitCastExpr *ICE = M.makeLvalueToRvalue(DR, Ty);
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/external/llvm/lib/Target/Hexagon/ |
H A D | RDFCopy.cpp | 66 RegisterRef DR = { DefR.Reg, S }; local 68 EM.insert(std::make_pair(DR, SR)); 183 RegisterRef DR = DA.Addr->getRegRef(); local 184 auto FR = EM.find(DR); 188 if (DR == SR) 200 if (UA.Addr->getRegRef() != DR) 212 dbgs() << "Can replace " << Print<RegisterRef>(DR, DFG) 239 if (J.second != DR)
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H A D | HexagonGenMux.cpp | 76 MuxInfo(MachineBasicBlock::iterator It, unsigned DR, unsigned PR, argument 79 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), 209 unsigned DR = MI->getOperand(0).getReg(); local 210 if (isRegPair(DR)) 215 CondsetMap::iterator F = CM.find(DR); 225 auto It = CM.insert(std::make_pair(DR, CondsetInfo())); 237 // There is now a complete definition of DR, i.e. we have the predicate 272 if (DU.Defs[PR] || DU.Defs[DR] || DU.Uses[DR]) { 289 ML.push_back(MuxInfo(At, DR, P [all...] |
H A D | HexagonExpandCondsets.cpp | 414 unsigned DR = Op.getReg(), DSR = Op.getSubReg(); 415 if (!TargetRegisterInfo::isVirtualRegister(DR) || DR != Reg) 417 LaneBitmask SLM = getLaneMask(DR, DSR); 655 unsigned DR = MD.getReg(), DSR = MD.getSubReg(); local 659 if (ReadUndef && DSR != 0 && MRI->shouldTrackSubRegLiveness(DR)) { 662 bool SameReg = (MS1.isReg() && DR == MS1.getReg()) || 663 (MS2.isReg() && DR == MS2.getReg()); 678 .addReg(DR, RegState::Define, NewSR); 687 genCondTfrFor(MI.getOperand(2), At, DR, DS [all...] |
H A D | HexagonGenPredicate.cpp | 454 Register DR = MI.getOperand(0); local 456 if (!TargetRegisterInfo::isVirtualRegister(DR.R)) 460 if (MRI->getRegClass(DR.R) != PredRC) 464 assert(!DR.S && !SR.S && "Unexpected subregister"); 465 MRI->replaceRegWith(DR.R, SR.R);
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H A D | HexagonSplitDouble.cpp | 380 for (unsigned DR : Part) { 381 MachineInstr *DefI = MRI->getVRegDef(DR); 387 if (isInduction(DR, IRM)) 390 for (auto U = MRI->use_nodbg_begin(DR), W = MRI->use_nodbg_end(); 778 // Shift left: DR = shl R, #s 782 // Shift right: DR = shr R, #s 893 // DR = or (R1, asl(R2, #s)) 901 // DR = or (R1, asl(R2, #0)) 930 // DR = or (R1, asl(R2, #32)) 940 // DR [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 53 DispRange DR; member in struct:__anon14513::SystemZAddressingMode 64 : Form(form), DR(dr), Base(), Disp(0), Index(), 162 // Try to match Addr as a FormBD address with displacement type DR. 165 bool selectBDAddr(SystemZAddressingMode::DispRange DR, SDValue Addr, 168 // Try to match Addr as a FormBDX address with displacement type DR. 171 bool selectMVIAddr(SystemZAddressingMode::DispRange DR, SDValue Addr, 175 // displacement type DR. Return true on success, storing the base, 178 SystemZAddressingMode::DispRange DR, SDValue Addr, 362 // with range DR. Here we're interested in the range of both the instruction 363 // described by DR an 364 selectDisp(SystemZAddressingMode::DispRange DR, int64_t Val) argument 475 isValidDisp(SystemZAddressingMode::DispRange DR, int64_t Val) argument 635 selectBDAddr(SystemZAddressingMode::DispRange DR, SDValue Addr, SDValue &Base, SDValue &Disp) const argument 646 selectMVIAddr(SystemZAddressingMode::DispRange DR, SDValue Addr, SDValue &Base, SDValue &Disp) const argument 657 selectBDXAddr(SystemZAddressingMode::AddrForm Form, SystemZAddressingMode::DispRange DR, SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument [all...] |
/external/clang/www/ |
H A D | make_cxx_dr_status | 16 class DR: class in inherits: 32 return DR(section, issue, url, status, title)
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/external/clang/include/clang/Analysis/Analyses/ |
H A D | LiveVariables.h | 66 virtual void observerKill(const DeclRefExpr *DR) {} argument
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/external/valgrind/VEX/priv/ |
H A D | host_mips_defs.h | 51 #define DR(_mode64, _enc, _ix64, _ix32) \ macro 81 return DR (mode64, 0, 0, 20); } 83 return DR (mode64, 2, 0, 21); } 85 return DR (mode64, 4, 0, 22); } 87 return DR (mode64, 6, 0, 23); } 89 return DR (mode64, 8, 0, 24); } 91 return DR (mode64, 10, 0, 25); } 93 return DR (mode64, 12, 0, 26); } 95 return DR (mode64, 14, 0, 27); } 120 #undef DR macro [all...] |
/external/llvm/tools/llvm-readobj/ |
H A D | MachODumper.cpp | 442 DataRefImpl DR = Section.getRawDataRefImpl(); local 447 ArrayRef<char> RawName = Obj->getSectionRawName(DR); 448 StringRef SegmentName = Obj->getSectionFinalSegmentName(DR); 449 ArrayRef<char> RawSegmentName = Obj->getSectionRawFinalSegmentName(DR); 534 DataRefImpl DR = Reloc.getRawDataRefImpl(); local 535 MachO::any_relocation_info RE = Obj->getRelocation(DR); 549 section_iterator SecI = Obj->getRelocationSection(DR);
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/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | CodeViewDebug.cpp | 712 LocalVarDefRange DR; local 713 DR.InMemory = -1; 714 DR.DataOffset = Offset; 715 assert(DR.DataOffset == Offset && "truncation"); 716 DR.StructOffset = 0; 717 DR.CVRegister = CVRegister; 718 return DR; 723 LocalVarDefRange DR; local 724 DR.InMemory = 0; 725 DR [all...] |