Searched refs:DSB (Results 1 - 17 of 17) sorted by relevance

/external/libavc/common/arm/
H A Dih264_arm_memory_barrier.s45 @* Description : Adds DSB
/external/llvm/test/MC/ARM/
H A Dinvalid-barrier.s14 @ DSB
H A Dbasic-arm-instructions-v8.s37 @ DSB (v8 barriers)
H A Dbasic-thumb2-instructions-v8.s67 @ DSB (ARMv8-only barriers)
H A Dbasic-arm-instructions.s880 @ DSB
H A Dbasic-thumb2-instructions.s607 @ DSB
/external/v8/src/arm64/
H A Ddisasm-arm64.cc1201 case DSB: {
H A Dconstants-arm64.h692 DSB = MemBarrierFixed | 0x00000000, enumerator in enum:v8::internal::MemBarrierOp
H A Dassembler-arm64.cc1815 Emit(DSB | ImmBarrierDomain(domain) | ImmBarrierType(type));
/external/vixl/src/aarch64/
H A Dconstants-aarch64.h737 DSB = MemBarrierFixed | 0x00000000, enumerator in enum:vixl::aarch64::MemBarrierOp
H A Ddisasm-aarch64.cc1767 case DSB: {
H A Dassembler-aarch64.cc2070 Emit(DSB | ImmBarrierDomain(domain) | ImmBarrierType(type));
/external/capstone/arch/ARM/
H A DARMGenAsmWriter.inc114 54010U, // DSB
2907 0U, // DSB
6128 // DMB, DSB
8781 // (DSB 15)
H A DARMGenInstrInfo.inc3291 { 97, 1, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #97 = DSB
/external/capstone/arch/AArch64/
H A DAArch64GenAsmWriter.inc290 29324U, // DSB
2682 0U, // DSB
5242 // DMB, DSB, ISB
/external/swiftshader/third_party/LLVM/test/MC/ARM/
H A Dbasic-arm-instructions.s547 @ DSB
H A Dbasic-thumb2-instructions.s418 @ DSB

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