Searched refs:FPToUInt32 (Results 1 - 5 of 5) sorted by relevance

/external/vixl/src/aarch64/
H A Dsimulator-aarch64.cc2262 WriteWRegister(dst, FPToUInt32(ReadSRegister(src), FPTieAway));
2268 WriteWRegister(dst, FPToUInt32(ReadDRegister(src), FPTieAway));
2286 WriteWRegister(dst, FPToUInt32(ReadSRegister(src), FPNegativeInfinity));
2292 WriteWRegister(dst, FPToUInt32(ReadDRegister(src), FPNegativeInfinity));
2310 WriteWRegister(dst, FPToUInt32(ReadSRegister(src), FPPositiveInfinity));
2316 WriteWRegister(dst, FPToUInt32(ReadDRegister(src), FPPositiveInfinity));
2334 WriteWRegister(dst, FPToUInt32(ReadSRegister(src), FPTieEven));
2340 WriteWRegister(dst, FPToUInt32(ReadDRegister(src), FPTieEven));
2358 WriteWRegister(dst, FPToUInt32(ReadSRegister(src), FPZero));
2364 WriteWRegister(dst, FPToUInt32(ReadDRegiste
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H A Dlogic-aarch64.cc3905 uint32_t Simulator::FPToUInt32(double value, FPRounding rmode) { function in class:vixl::aarch64::Simulator
4492 dst.SetUint(vform, i, FPToUInt32(op, rounding_mode));
H A Dsimulator-aarch64.h3005 uint32_t FPToUInt32(double value, FPRounding rmode);
/external/v8/src/arm64/
H A Dsimulator-arm64.cc2268 case FCVTAU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieAway)); break;
2270 case FCVTAU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieAway)); break;
2285 set_wreg(dst, FPToUInt32(sreg(src), FPNegativeInfinity));
2291 set_wreg(dst, FPToUInt32(dreg(src), FPNegativeInfinity));
2300 case FCVTNU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieEven)); break;
2302 case FCVTNU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieEven)); break;
2308 case FCVTZU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPZero)); break;
2310 case FCVTZU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPZero)); break;
2406 uint32_t Simulator::FPToUInt32(double value, FPRounding rmode) {
H A Dsimulator-arm64.h721 uint32_t FPToUInt32(double value, FPRounding rmode);

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