Searched refs:FPToUInt64 (Results 1 - 5 of 5) sorted by relevance

/external/vixl/src/aarch64/
H A Dsimulator-aarch64.cc2265 WriteXRegister(dst, FPToUInt64(ReadSRegister(src), FPTieAway));
2271 WriteXRegister(dst, FPToUInt64(ReadDRegister(src), FPTieAway));
2289 WriteXRegister(dst, FPToUInt64(ReadSRegister(src), FPNegativeInfinity));
2295 WriteXRegister(dst, FPToUInt64(ReadDRegister(src), FPNegativeInfinity));
2313 WriteXRegister(dst, FPToUInt64(ReadSRegister(src), FPPositiveInfinity));
2319 WriteXRegister(dst, FPToUInt64(ReadDRegister(src), FPPositiveInfinity));
2337 WriteXRegister(dst, FPToUInt64(ReadSRegister(src), FPTieEven));
2343 WriteXRegister(dst, FPToUInt64(ReadDRegister(src), FPTieEven));
2361 WriteXRegister(dst, FPToUInt64(ReadSRegister(src), FPZero));
2367 WriteXRegister(dst, FPToUInt64(ReadDRegiste
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H A Dlogic-aarch64.cc3916 uint64_t Simulator::FPToUInt64(double value, FPRounding rmode) { function in class:vixl::aarch64::Simulator
4498 dst.SetUint(vform, i, FPToUInt64(op, rounding_mode));
H A Dsimulator-aarch64.h3006 uint64_t FPToUInt64(double value, FPRounding rmode);
/external/v8/src/arm64/
H A Dsimulator-arm64.cc2269 case FCVTAU_xs: set_xreg(dst, FPToUInt64(sreg(src), FPTieAway)); break;
2271 case FCVTAU_xd: set_xreg(dst, FPToUInt64(dreg(src), FPTieAway)); break;
2288 set_xreg(dst, FPToUInt64(sreg(src), FPNegativeInfinity));
2294 set_xreg(dst, FPToUInt64(dreg(src), FPNegativeInfinity));
2301 case FCVTNU_xs: set_xreg(dst, FPToUInt64(sreg(src), FPTieEven)); break;
2303 case FCVTNU_xd: set_xreg(dst, FPToUInt64(dreg(src), FPTieEven)); break;
2309 case FCVTZU_xs: set_xreg(dst, FPToUInt64(sreg(src), FPZero)); break;
2311 case FCVTZU_xd: set_xreg(dst, FPToUInt64(dreg(src), FPZero)); break;
2417 uint64_t Simulator::FPToUInt64(double value, FPRounding rmode) {
H A Dsimulator-arm64.h722 uint64_t FPToUInt64(double value, FPRounding rmode);

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