/external/vixl/test/aarch32/ |
H A D | test-assembler-cond-rd-operand-rn-shift-amount-1to31-in-it-block-t32.cc | 96 {{{hi, r2, r4, LSL, 10}, true, hi, "hi r2 r4 LSL 10", "hi_r2_r4_LSL_10"}, 97 {{cs, r6, r2, LSL, 8}, true, cs, "cs r6 r2 LSL 8", "cs_r6_r2_LSL_8"}, 98 {{lt, r5, r3, LSL, 21}, true, lt, "lt r5 r3 LSL 21", "lt_r5_r3_LSL_21"}, 99 {{ge, r5, r0, LSL, 3}, true, ge, "ge r5 r0 LSL 3", "ge_r5_r0_LSL_3"}, 100 {{mi, r4, r1, LSL, 4}, true, mi, "mi r4 r1 LSL [all...] |
H A D | test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 116 const TestData kTests[] = {{{eq, r13, r13, r0, LSL, 5}, 119 "eq r13 r13 r0 LSL 5", 121 {{mi, r10, r14, r13, LSL, 10}, 124 "mi r10 r14 r13 LSL 10", 126 {{hi, r6, r2, r13, LSL, 4}, 129 "hi r6 r2 r13 LSL 4", 131 {{ge, r3, r5, r13, LSL, 2}, 134 "ge r3 r5 r13 LSL 2", 146 {{pl, r11, r1, r7, LSL, 23}, 149 "pl r11 r1 r7 LSL 2 [all...] |
H A D | test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 116 const TestData kTests[] = {{{al, r12, r4, r7, LSL, 7}, 119 "al r12 r4 r7 LSL 7", 131 {{al, r14, r13, r10, LSL, 22}, 134 "al r14 r13 r10 LSL 22", 141 {{al, r14, r11, r5, LSL, 15}, 144 "al r14 r11 r5 LSL 15", 146 {{al, r2, r2, r7, LSL, 28}, 149 "al r2 r2 r7 LSL 28", 156 {{al, r11, r2, r8, LSL, 4}, 159 "al r11 r2 r8 LSL [all...] |
H A D | test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 108 {{al, r2, r6, LSL, 30}, false, al, "al r2 r6 LSL 30", "al_r2_r6_LSL_30"}, 109 {{al, r11, r4, LSL, 26}, false, al, "al r11 r4 LSL 26", "al_r11_r4_LSL_26"}, 110 {{al, r7, r0, LSL, 30}, false, al, "al r7 r0 LSL 30", "al_r7_r0_LSL_30"}, 114 {{al, r11, r13, LSL, 24}, 117 "al r11 r13 LSL 24", 122 {{al, r2, r6, LSL, 7}, false, al, "al r2 r6 LSL [all...] |
H A D | test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc | 109 {{hi, r7, r1, LSL, 29}, false, al, "hi r7 r1 LSL 29", "hi_r7_r1_LSL_29"}, 112 {{lt, r1, r1, LSL, 23}, false, al, "lt r1 r1 LSL 23", "lt_r1_r1_LSL_23"}, 118 {{cs, r3, r5, LSL, 8}, false, al, "cs r3 r5 LSL 8", "cs_r3_r5_LSL_8"}, 119 {{gt, r0, r13, LSL, 23}, false, al, "gt r0 r13 LSL 23", "gt_r0_r13_LSL_23"}, 123 {{ls, r3, r5, LSL, 20}, false, al, "ls r3 r5 LSL 2 [all...] |
H A D | test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc | 102 const TestData kTests[] = {{{pl, r8, r11, plus, r6, LSL, 1, Offset}, 105 "pl r8 r11 plus r6 LSL 1 Offset", 107 {{le, r4, r8, plus, r5, LSL, 1, Offset}, 110 "le r4 r8 plus r5 LSL 1 Offset", 112 {{vs, r2, r6, plus, r14, LSL, 1, Offset}, 115 "vs r2 r6 plus r14 LSL 1 Offset", 117 {{ls, r1, r7, plus, r8, LSL, 1, Offset}, 120 "ls r1 r7 plus r8 LSL 1 Offset", 122 {{ge, r14, r6, plus, r14, LSL, 1, Offset}, 125 "ge r14 r6 plus r14 LSL [all...] |
H A D | test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc | 258 {{{eq, r0, r1, plus, r8, LSL, 1, Offset}, 259 "eq r0 r1 plus r8 LSL 1 Offset", 263 {{ne, r0, r1, plus, r8, LSL, 1, Offset}, 264 "ne r0 r1 plus r8 LSL 1 Offset", 268 {{cs, r0, r1, plus, r8, LSL, 1, Offset}, 269 "cs r0 r1 plus r8 LSL 1 Offset", 273 {{cc, r0, r1, plus, r8, LSL, 1, Offset}, 274 "cc r0 r1 plus r8 LSL 1 Offset", 278 {{mi, r0, r1, plus, r8, LSL, 1, Offset}, 279 "mi r0 r1 plus r8 LSL [all...] |
H A D | test-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc | 96 {{{ge, r1, r1, LSL, r6}, true, ge, "ge r1 r1 LSL r6", "ge_r1_r1_LSL_r6"}, 97 {{cs, r7, r7, LSL, r2}, true, cs, "cs r7 r7 LSL r2", "cs_r7_r7_LSL_r2"}, 98 {{gt, r1, r1, LSL, r0}, true, gt, "gt r1 r1 LSL r0", "gt_r1_r1_LSL_r0"}, 101 {{vs, r2, r2, LSL, r0}, true, vs, "vs r2 r2 LSL r0", "vs_r2_r2_LSL_r0"}, 106 {{le, r7, r7, LSL, r0}, true, le, "le r7 r7 LSL r [all...] |
H A D | test-assembler-cond-rd-operand-rn-shift-rs-a32.cc | 104 {{gt, r13, r11, LSL, r12}, 107 "gt r13 r11 LSL r12", 116 {{al, r9, r10, LSL, r4}, false, al, "al r9 r10 LSL r4", "al_r9_r10_LSL_r4"}, 122 {{gt, r9, r11, LSL, r12}, 125 "gt r9 r11 LSL r12", 137 {{cc, r6, r3, LSL, r2}, false, al, "cc r6 r3 LSL r2", "cc_r6_r3_LSL_r2"}, 158 {{ne, r6, r3, LSL, r2}, false, al, "ne r6 r3 LSL r [all...] |
H A D | test-assembler-cond-rd-operand-rn-shift-rs-narrow-out-it-block-t32.cc | 96 {{{al, r0, r0, LSL, r0}, false, al, "al r0 r0 LSL r0", "al_r0_r0_LSL_r0"}, 97 {{al, r0, r0, LSL, r1}, false, al, "al r0 r0 LSL r1", "al_r0_r0_LSL_r1"}, 98 {{al, r0, r0, LSL, r2}, false, al, "al r0 r0 LSL r2", "al_r0_r0_LSL_r2"}, 99 {{al, r0, r0, LSL, r3}, false, al, "al r0 r0 LSL r3", "al_r0_r0_LSL_r3"}, 100 {{al, r0, r0, LSL, r4}, false, al, "al r0 r0 LSL r [all...] |
H A D | test-assembler-negative-cond-rd-rn-operand-rm-shift-rs-a32.cc | 112 {{gt, r15, r8, r15, LSL, r10}, 113 "gt, r15, r8, r15, LSL, r10", 115 {{vc, r10, r14, r15, LSL, r1}, 116 "vc, r10, r14, r15, LSL, r1", 133 {{cs, r15, r14, r15, LSL, r3}, 134 "cs, r15, r14, r15, LSL, r3", 136 {{vc, r15, r9, r7, LSL, r4}, 137 "vc, r15, r9, r7, LSL, r4", 151 {{lt, r2, r11, r15, LSL, r0}, 152 "lt, r2, r11, r15, LSL, r [all...] |
H A D | test-assembler-cond-rd-operand-rn-shift-rs-t32.cc | 116 {{al, r5, r13, LSL, r14}, 119 "al r5 r13 LSL r14", 145 {{al, r4, r6, LSL, r6}, false, al, "al r4 r6 LSL r6", "al_r4_r6_LSL_r6"}, 146 {{al, r13, r0, LSL, r2}, false, al, "al r13 r0 LSL r2", "al_r13_r0_LSL_r2"}, 154 {{al, r1, r12, LSL, r5}, false, al, "al r1 r12 LSL r5", "al_r1_r12_LSL_r5"}, 162 {{al, r6, r10, LSL, r14}, 165 "al r6 r10 LSL r1 [all...] |
H A D | test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc | 116 const TestData kTests[] = {{{mi, r8, r10, r8, LSL, r0}, 119 "mi r8 r10 r8 LSL r0", 141 {{pl, r10, r12, r5, LSL, r5}, 144 "pl r10 r12 r5 LSL r5", 146 {{ls, r10, r2, r2, LSL, r9}, 149 "ls r10 r2 r2 LSL r9", 171 {{cc, r7, r1, r14, LSL, r0}, 174 "cc r7 r1 r14 LSL r0", 201 {{lt, r12, r4, r6, LSL, r5}, 204 "lt r12 r4 r6 LSL r [all...] |
H A D | test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc | 323 const TestLoopData kTests[] = {{{eq, r0, r0, LSL, 1}, 324 "eq r0 r0 LSL 1", 328 {{ne, r0, r0, LSL, 1}, 329 "ne r0 r0 LSL 1", 333 {{cs, r0, r0, LSL, 1}, 334 "cs r0 r0 LSL 1", 338 {{cc, r0, r0, LSL, 1}, 339 "cc r0 r0 LSL 1", 343 {{mi, r0, r0, LSL, 1}, 344 "mi r0 r0 LSL [all...] |
H A D | test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 323 const TestLoopData kTests[] = {{{eq, r0, r0, LSL, 1}, 324 "eq r0 r0 LSL 1", 328 {{ne, r0, r0, LSL, 1}, 329 "ne r0 r0 LSL 1", 333 {{cs, r0, r0, LSL, 1}, 334 "cs r0 r0 LSL 1", 338 {{cc, r0, r0, LSL, 1}, 339 "cc r0 r0 LSL 1", 343 {{mi, r0, r0, LSL, 1}, 344 "mi r0 r0 LSL [all...] |
/external/libxaac/decoder/armv7/ |
H A D | ixheaacd_shiftrountine_with_round_hq.s | 10 ADD r12, r2, r3, LSL #2 16 LDR r5, [r1, r3, LSL #2] 17 LDR r7, [r0, r3, LSL #2] 41 MOVEQ r4, r4, LSL #6 47 MOVEQ r5, r5, LSL #6 57 MOVEQ r6, r6, LSL #6 64 MOVEQ r7, r7, LSL #6
|
H A D | ixheaacd_mps_synt_out_calc.s | 18 ADD R4, R1, R0, LSL #2 19 ADD R5, R2, R7, LSL #2 45 ADD R1, R1, R0, LSL #2 46 ADD R4, R4, R0, LSL #2 47 ADD R2, R2, R7, LSL #2 48 ADD R5, R5, R7, LSL #2
|
H A D | ixheaacd_eld_decoder_sbr_pre_twiddle.s | 20 LSL r8, r8, #1 @Left shift the multiplied value by 1 24 ADD r12, r8, r10, LSL #1 @mac32x16in32_shl( mult32x16in32_shl(Xre, cosine) , mult32x16in32_shl( Xim , sine))@ 33 LSL r9, r9, #1 @Left shift the multiplied value by 1 37 SUB r14, r9, r7, LSL #1 @sub32(mult32x16in32_shl(Xim, cosine) , mult32x16in32_shl(Xre, sine)) 48 LSL r8, r8, #1 52 ADD r12, r8, r10, LSL #1 56 LSL r9, r9, #1 60 SUB r14, r9, r7, LSL #1
|
H A D | ixheaacd_rescale_subbandsamples.s | 37 ADD R9, R0, R5, LSL#2 55 ADD R10, R10, R2, LSL #2 63 MOV R11, R11, LSL R4 66 MOVGE R5, R5, LSL R4 81 ADD R10, R10, R2, LSL #2 106 ADD R5, R1, R5, LSL#2 112 ADD R10, R10, R2, LSL #2 113 ADD R8, R8, R2, LSL #2 119 MOV R11, R11, LSL R4 120 MOV R1, R1, LSL R [all...] |
H A D | ixheaacd_harm_idx_zerotwolp.s | 53 MOVGT r8, r7, LSL r8 55 MOVS r12, r12, LSL #16 67 LDR r7, [r9, r2, LSL #2] 68 ADD r12, r10, r2, LSL #2 72 ADD r8, r8, r7, LSL #1 93 MOVPL r12, r7, LSL r9 95 MOV r7, r10, LSL #16
|
H A D | ixheaacd_shiftrountine_with_round.s | 31 ADD r12, r2, r3, LSL #1 37 LDR r5, [r1, r3, LSL #2] 38 LDR r7, [r0, r3, LSL #2] 62 MOVEQ r4, r4, LSL #10 70 MOVEQ r5, r5, LSL #10 82 MOVEQ r6, r6, LSL #10 90 MOVEQ r7, r7, LSL #10
|
H A D | ixheaacd_enery_calc_per_subband.s | 36 ADD r10, r10, r12, LSL #1 39 MOV R1, R1, LSL #1 55 ADD R0, R0, R4, LSL #2 56 ADD R0, R0, R2, LSL #8 64 ADD R0, R0, R4, LSL #2 65 ADD R0, R0, R2, LSL #9 67 MOV R2, R2, LSL #1 119 MOV R4, R4, LSL R12 121 MOV R3, R3, LSL R12 137 ADD R12, R12, R14, LSL# [all...] |
H A D | ixheaacd_shiftrountine_with_rnd_eld.s | 8 ADD r12, r2, r3, LSL #1 14 LDR r5, [r1, r3, LSL #2] @i2 = qmfImag[j] 15 LDR r7, [r0, r3, LSL #2] @r2 = qmfReal[j] 33 @STR r7,[r1,r3,LSL #2] 34 @STR r5,[r0,r3,LSL #2] 48 MOVEQ r4, r4, LSL #9 @shift by 9(hardcoded value) if not AAC_ELD left shifted by 10 56 MOVEQ r5, r5, LSL #9 68 MOVEQ r6, r6, LSL #9 76 MOVEQ r7, r7, LSL #9
|
H A D | ixheaacd_expsubbandsamples.s | 47 ADD r0, r0, r7, LSL #2 52 ADD r5, r1, r2, LSL #2 74 LDR r6, [r0, r7, LSL #2] 75 LDR r5, [r1, r7, LSL #2] 76 ADD r6, r6, r2, LSL #2 77 ADD r5, r5, r2, LSL #2
|
H A D | ixheaacd_complex_fft_p2.s | 20 MOV lr, r0, LSL #1 @(npoints >>1) * 4 28 ORR r4, r7, r6, LSL #2 31 ORR r4, r7, r6, LSL #4 35 ORR r4, r7, r6, LSL #8 42 ADD r1, r2, r10, LSL #2 78 SUB r3, r3, r0, LSL #3 92 MOV r0, r0, LSL #3 @(del<<1) * 4 160 MOV r0, r0, LSL #3 @(del<<1) * 4 161 LDR r1, [r3, r4, LSL #3]! @ w1h = *(twiddles + 2*j)@ 163 LDR r5, [r3, r4, LSL # [all...] |