| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonEarlyIfConv.cpp | 106 FlowPattern() : SplitB(0), TrueB(0), FalseB(0), JoinB(0), PredR(0) {}
109 : SplitB(B), TrueB(TB), FalseB(FB), JoinB(JB), PredR(PR) {}
113 unsigned PredR; member in struct:__anon14328::FlowPattern
126 << ", PredR:" << PrintReg(P.FP.PredR, &P.TRI)
174 MachineInstr *MI, unsigned PredR, bool IfTrue);
177 unsigned PredR, bool IfTrue);
227 unsigned PredR = T1I->getOperand(0).getReg(); local
248 // Record the true/false blocks in such a way that "true" means "if (PredR)",
249 // and "false" means "if (!PredR)"
706 predicateInstr(MachineBasicBlock *ToB, MachineBasicBlock::iterator At, MachineInstr *MI, unsigned PredR, bool IfTrue) argument
755 predicateBlockNB(MachineBasicBlock *ToB, MachineBasicBlock::iterator At, MachineBasicBlock *FromB, unsigned PredR, bool IfTrue) argument
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| H A D | HexagonGenMux.cpp | 62 unsigned PredR; member in struct:__anon14344::HexagonGenMux::CondsetInfo
64 CondsetInfo() : PredR(0), TrueX(UINT_MAX), FalseX(UINT_MAX) {}
73 unsigned DefR, PredR; member in struct:__anon14344::HexagonGenMux::MuxInfo
79 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1),
220 if (F != CM.end() && F->second.PredR != PR) {
227 F->second.PredR = PR;
300 .addReg(MX.PredR)
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| H A D | HexagonExpandCondsets.cpp | 258 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
265 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
740 /// under the conditions given by PredR and Cond, and this function will ignore
743 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) {
756 if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(*MI)))
760 // Check the defs. If the PredR is defined, invalidate it. If RD is
766 if (RR.Reg == PredR) {
853 /// PredR and Cond) at the point indicated by Where.
917 unsigned PredR, bool Cond, MachineBasicBlock::iterator First,
926 if (!MI->readsRegister(PredR) || (Con
742 getReachingDefForPred(RegisterRef RD, MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) argument
916 renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR, bool Cond, MachineBasicBlock::iterator First, MachineBasicBlock::iterator Last) argument
967 unsigned PredR = MP.getReg(); local
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| H A D | HexagonHardwareLoops.cpp | 443 unsigned PredR, PredPos, PredRegFlags; local
444 if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags))
447 MachineInstr *PredI = MRI->getVRegDef(PredR);
1298 unsigned PredR = CmpI->getOperand(0).getReg(); local
1306 if (MO.getReg() == PredR) // Found an intervening use of PredR.
1877 unsigned PredR = PN->getOperand(i).getReg(); local
1883 MachineOperand MO = MachineOperand::CreateReg(PredR, false);
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| H A D | HexagonBitSimplify.cpp | 2692 unsigned PredR = 0;
2693 if (!isSameShuffle(G.Out.Reg, G.Inp.Reg, F->PR.Reg, PredR)) {
2704 PredR = MRI->createVirtualRegister(RC);
2709 BuildMI(*C.PB, T, DL, HII->get(TfrI), PredR)
2712 PredR = F->PR.Reg;
2715 assert(MRI->getRegClass(PredR) == MRI->getRegClass(G.Inp.Reg));
2716 moveGroup(G, *F->LB, *F->PB, F->LB->getFirstNonPHI(), F->DefR, PredR);
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| H A D | HexagonISelLowering.cpp | 636 unsigned PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass); local
637 SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR,
640 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1,
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