Searched refs:ROR (Results 1 - 25 of 100) sorted by relevance

1234

/external/vixl/test/aarch32/
H A Dtest-assembler-cond-rd-operand-rn-ror-amount-t32.cc102 {{al, r0, r0, ROR, 0}, false, al, "al r0 r0 ROR 0", "al_r0_r0_ROR_0"},
103 {{al, r0, r0, ROR, 8}, false, al, "al r0 r0 ROR 8", "al_r0_r0_ROR_8"},
104 {{al, r0, r0, ROR, 16}, false, al, "al r0 r0 ROR 16", "al_r0_r0_ROR_16"},
105 {{al, r0, r0, ROR, 24}, false, al, "al r0 r0 ROR 24", "al_r0_r0_ROR_24"},
106 {{al, r0, r1, ROR, 0}, false, al, "al r0 r1 ROR
[all...]
H A Dtest-assembler-cond-rd-operand-rn-ror-amount-a32.cc102 {{vc, r2, r5, ROR, 0}, false, al, "vc r2 r5 ROR 0", "vc_r2_r5_ROR_0"},
103 {{eq, r5, r7, ROR, 0}, false, al, "eq r5 r7 ROR 0", "eq_r5_r7_ROR_0"},
104 {{ge, r3, r2, ROR, 8}, false, al, "ge r3 r2 ROR 8", "ge_r3_r2_ROR_8"},
105 {{cc, r11, r3, ROR, 16}, false, al, "cc r11 r3 ROR 16", "cc_r11_r3_ROR_16"},
106 {{cs, r13, r6, ROR, 0}, false, al, "cs r13 r6 ROR
[all...]
H A Dtest-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc102 const TestData kTests[] = {{{ls, r3, r3, r13, ROR, 0},
105 "ls r3 r3 r13 ROR 0",
107 {{cs, r2, r7, r1, ROR, 16},
110 "cs r2 r7 r1 ROR 16",
112 {{mi, r13, r0, r2, ROR, 8},
115 "mi r13 r0 r2 ROR 8",
117 {{lt, r0, r6, r1, ROR, 8},
120 "lt r0 r6 r1 ROR 8",
122 {{al, r6, r4, r8, ROR, 16},
125 "al r6 r4 r8 ROR 1
[all...]
H A Dtest-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc102 const TestData kTests[] = {{{al, r4, r0, r8, ROR, 16},
105 "al r4 r0 r8 ROR 16",
107 {{al, r14, r13, r12, ROR, 24},
110 "al r14 r13 r12 ROR 24",
112 {{al, r9, r10, r5, ROR, 16},
115 "al r9 r10 r5 ROR 16",
117 {{al, r11, r13, r14, ROR, 8},
120 "al r11 r13 r14 ROR 8",
122 {{al, r3, r12, r11, ROR, 16},
125 "al r3 r12 r11 ROR 1
[all...]
H A Dtest-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc121 {{al, r7, r8, r10, ROR, 21},
124 "al r7 r8 r10 ROR 21",
126 {{al, r5, r5, r3, ROR, 12},
129 "al r5 r5 r3 ROR 12",
136 {{al, r9, r10, r11, ROR, 2},
139 "al r9 r10 r11 ROR 2",
151 {{al, r2, r11, r1, ROR, 9},
154 "al r2 r11 r1 ROR 9",
161 {{al, r6, r13, r3, ROR, 1},
164 "al r6 r13 r3 ROR
[all...]
H A Dtest-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc136 {{cc, r10, r5, r1, ROR, 10},
139 "cc r10 r5 r1 ROR 10",
141 {{ge, r3, r14, r7, ROR, 7},
144 "ge r3 r14 r7 ROR 7",
171 {{cs, r12, r3, r0, ROR, 20},
174 "cs r12 r3 r0 ROR 20",
176 {{vs, r1, r6, r9, ROR, 14},
179 "vs r1 r6 r9 ROR 14",
186 {{vc, r14, r13, r10, ROR, 7},
189 "vc r14 r13 r10 ROR
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc104 {{vc, r5, r5, ROR, 10}, false, al, "vc r5 r5 ROR 10", "vc_r5_r5_ROR_10"},
105 {{ne, r3, r4, ROR, 17}, false, al, "ne r3 r4 ROR 17", "ne_r3_r4_ROR_17"},
106 {{cs, r9, r10, ROR, 16}, false, al, "cs r9 r10 ROR 16", "cs_r9_r10_ROR_16"},
107 {{lt, r0, r2, ROR, 29}, false, al, "lt r0 r2 ROR 29", "lt_r0_r2_ROR_29"},
108 {{al, r11, r2, ROR, 23}, false, al, "al r11 r2 ROR 2
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc104 {{al, r14, r8, ROR, 21}, false, al, "al r14 r8 ROR 21", "al_r14_r8_ROR_21"},
105 {{al, r5, r13, ROR, 4}, false, al, "al r5 r13 ROR 4", "al_r5_r13_ROR_4"},
106 {{al, r0, r3, ROR, 4}, false, al, "al r0 r3 ROR 4", "al_r0_r3_ROR_4"},
107 {{al, r3, r14, ROR, 7}, false, al, "al r3 r14 ROR 7", "al_r3_r14_ROR_7"},
111 {{al, r0, r9, ROR, 17}, false, al, "al r0 r9 ROR 1
[all...]
H A Dtest-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc602 {{al, r0, r2, plus, r14, ROR, 9, Offset},
605 "al r0 r2 plus r14 ROR 9 Offset",
617 {{al, r0, r4, plus, r12, ROR, 13, Offset},
620 "al r0 r4 plus r12 ROR 13 Offset",
627 {{al, r0, r7, plus, r0, ROR, 25, Offset},
630 "al r0 r7 plus r0 ROR 25 Offset",
647 {{al, r0, r7, plus, r12, ROR, 11, Offset},
650 "al r0 r7 plus r12 ROR 11 Offset",
677 {{al, r0, r8, minus, r7, ROR, 30, Offset},
680 "al r0 r8 minus r7 ROR 3
[all...]
H A Dtest-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc348 {{al, r4, r12, plus, r9, ROR, 12, Offset},
349 "al r4 r12 plus r9 ROR 12 Offset",
378 {{al, r0, r11, plus, r4, ROR, 2, Offset},
379 "al r0 r11 plus r4 ROR 2 Offset",
388 {{al, r2, r11, plus, r9, ROR, 29, Offset},
389 "al r2 r11 plus r9 ROR 29 Offset",
408 {{al, r5, r1, plus, r3, ROR, 19, Offset},
409 "al r5 r1 plus r3 ROR 19 Offset",
428 {{al, r7, r14, plus, r0, ROR, 17, Offset},
429 "al r7 r14 plus r0 ROR 1
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-rs-a32.cc110 {{ge, r11, r13, ROR, r2},
113 "ge r11 r13 ROR r2",
121 {{eq, r3, r0, ROR, r11}, false, al, "eq r3 r0 ROR r11", "eq_r3_r0_ROR_r11"},
127 {{ge, r14, r6, ROR, r13},
130 "ge r14 r6 ROR r13",
138 {{ge, r4, r6, ROR, r7}, false, al, "ge r4 r6 ROR r7", "ge_r4_r6_ROR_r7"},
160 {{hi, r9, r11, ROR, r13},
163 "hi r9 r11 ROR r1
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-rs-t32.cc111 {{al, r12, r3, ROR, r5}, false, al, "al r12 r3 ROR r5", "al_r12_r3_ROR_r5"},
133 {{al, r12, r11, ROR, r7},
136 "al r12 r11 ROR r7",
143 {{al, r11, r7, ROR, r0}, false, al, "al r11 r7 ROR r0", "al_r11_r7_ROR_r0"},
144 {{al, r6, r13, ROR, r2}, false, al, "al r6 r13 ROR r2", "al_r6_r13_ROR_r2"},
155 {{al, r4, r2, ROR, r3}, false, al, "al r4 r2 ROR r
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-rs-narrow-out-it-block-t32.cc120 {{al, r0, r0, ROR, r0}, false, al, "al r0 r0 ROR r0", "al_r0_r0_ROR_r0"},
121 {{al, r0, r0, ROR, r1}, false, al, "al r0 r0 ROR r1", "al_r0_r0_ROR_r1"},
122 {{al, r0, r0, ROR, r2}, false, al, "al r0 r0 ROR r2", "al_r0_r0_ROR_r2"},
123 {{al, r0, r0, ROR, r3}, false, al, "al r0 r0 ROR r3", "al_r0_r0_ROR_r3"},
124 {{al, r0, r0, ROR, r4}, false, al, "al r0 r0 ROR r
[all...]
H A Dtest-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc121 {{cc, r11, r4, r13, ROR, r8},
124 "cc r11 r4 r13 ROR r8",
126 {{al, r13, r11, r3, ROR, r4},
129 "al r13 r11 r3 ROR r4",
136 {{vs, r12, r0, r8, ROR, r13},
139 "vs r12 r0 r8 ROR r13",
156 {{mi, r3, r13, r0, ROR, r11},
159 "mi r3 r13 r0 ROR r11",
166 {{le, r12, r8, r14, ROR, r1},
169 "le r12 r8 r14 ROR r
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc99 {{pl, r3, r3, ROR, r3}, true, pl, "pl r3 r3 ROR r3", "pl_r3_r3_ROR_r3"},
100 {{vc, r4, r4, ROR, r1}, true, vc, "vc r4 r4 ROR r1", "vc_r4_r4_ROR_r1"},
104 {{hi, r6, r6, ROR, r5}, true, hi, "hi r6 r6 ROR r5", "hi_r6_r6_ROR_r5"},
116 {{eq, r5, r5, ROR, r2}, true, eq, "eq r5 r5 ROR r2", "eq_r5_r5_ROR_r2"},
122 {{ge, r6, r6, ROR, r3}, true, ge, "ge r6 r6 ROR r
[all...]
H A Dtest-assembler-negative-cond-rd-rn-operand-rm-shift-rs-a32.cc121 {{eq, r9, r15, r1, ROR, r1},
122 "eq, r9, r15, r1, ROR, r1",
127 {{ge, r15, r5, r13, ROR, r5},
128 "ge, r15, r5, r13, ROR, r5",
145 {{mi, r15, r3, r8, ROR, r6},
146 "mi, r15, r3, r8, ROR, r6",
160 {{vc, r0, r8, r5, ROR, r15},
161 "vc, r0, r8, r5, ROR, r15",
169 {{le, r15, r15, r3, ROR, r2},
170 "le, r15, r15, r3, ROR, r
[all...]
H A Dtest-simulator-cond-rd-operand-rn-ror-amount-a32.cc321 const TestLoopData kTests[] = {{{eq, r0, r0, ROR, 0},
322 "eq r0 r0 ROR 0",
326 {{ne, r0, r0, ROR, 0},
327 "ne r0 r0 ROR 0",
331 {{cs, r0, r0, ROR, 0},
332 "cs r0 r0 ROR 0",
336 {{cc, r0, r0, ROR, 0},
337 "cc r0 r0 ROR 0",
341 {{mi, r0, r0, ROR, 0},
342 "mi r0 r0 ROR
[all...]
H A Dtest-simulator-cond-rd-operand-rn-ror-amount-t32.cc321 const TestLoopData kTests[] = {{{eq, r0, r0, ROR, 0},
322 "eq r0 r0 ROR 0",
326 {{ne, r0, r0, ROR, 0},
327 "ne r0 r0 ROR 0",
331 {{cs, r0, r0, ROR, 0},
332 "cs r0 r0 ROR 0",
336 {{cc, r0, r0, ROR, 0},
337 "cc r0 r0 ROR 0",
341 {{mi, r0, r0, ROR, 0},
342 "mi r0 r0 ROR
[all...]
H A Dtest-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc673 {{al, r0, r0, ROR, 1},
674 "al r0 r0 ROR 1",
678 {{al, r0, r0, ROR, 2},
679 "al r0 r0 ROR 2",
683 {{al, r0, r0, ROR, 3},
684 "al r0 r0 ROR 3",
688 {{al, r0, r0, ROR, 4},
689 "al r0 r0 ROR 4",
693 {{al, r0, r0, ROR, 5},
694 "al r0 r0 ROR
[all...]
H A Dtest-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc673 {{al, r0, r1, ROR, 1},
674 "al r0 r1 ROR 1",
678 {{al, r0, r1, ROR, 2},
679 "al r0 r1 ROR 2",
683 {{al, r0, r1, ROR, 3},
684 "al r0 r1 ROR 3",
688 {{al, r0, r1, ROR, 4},
689 "al r0 r1 ROR 4",
693 {{al, r0, r1, ROR, 5},
694 "al r0 r1 ROR
[all...]
H A Dtest-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc823 const TestLoopData kTests[] = {{{eq, r0, r0, r0, ROR, 0},
824 "eq r0 r0 r0 ROR 0",
828 {{ne, r0, r0, r0, ROR, 0},
829 "ne r0 r0 r0 ROR 0",
833 {{cs, r0, r0, r0, ROR, 0},
834 "cs r0 r0 r0 ROR 0",
838 {{cc, r0, r0, r0, ROR, 0},
839 "cc r0 r0 r0 ROR 0",
843 {{mi, r0, r0, r0, ROR, 0},
844 "mi r0 r0 r0 ROR
[all...]
H A Dtest-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc823 const TestLoopData kTests[] = {{{eq, r0, r0, r0, ROR, 0},
824 "eq r0 r0 r0 ROR 0",
828 {{ne, r0, r0, r0, ROR, 0},
829 "ne r0 r0 r0 ROR 0",
833 {{cs, r0, r0, r0, ROR, 0},
834 "cs r0 r0 r0 ROR 0",
838 {{cc, r0, r0, r0, ROR, 0},
839 "cc r0 r0 r0 ROR 0",
843 {{mi, r0, r0, r0, ROR, 0},
844 "mi r0 r0 r0 ROR
[all...]
H A Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc1217 {{al, r0, r0, r1, ROR, 1},
1218 "al r0 r0 r1 ROR 1",
1222 {{al, r0, r0, r1, ROR, 2},
1223 "al r0 r0 r1 ROR 2",
1227 {{al, r0, r0, r1, ROR, 3},
1228 "al r0 r0 r1 ROR 3",
1232 {{al, r0, r0, r1, ROR, 4},
1233 "al r0 r0 r1 ROR 4",
1237 {{al, r0, r0, r1, ROR, 5},
1238 "al r0 r0 r1 ROR
[all...]
H A Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc1217 {{al, r0, r1, r2, ROR, 1},
1218 "al r0 r1 r2 ROR 1",
1222 {{al, r0, r1, r2, ROR, 2},
1223 "al r0 r1 r2 ROR 2",
1227 {{al, r0, r1, r2, ROR, 3},
1228 "al r0 r1 r2 ROR 3",
1232 {{al, r0, r1, r2, ROR, 4},
1233 "al r0 r1 r2 ROR 4",
1237 {{al, r0, r1, r2, ROR, 5},
1238 "al r0 r1 r2 ROR
[all...]
/external/vixl/src/aarch32/
H A Dinstructions-aarch32.cc49 case ROR:
428 case ROR:
592 case ROR:
730 case ROR:

Completed in 954 milliseconds

1234