/external/llvm/lib/CodeGen/ |
H A D | DetectDeadLanes.cpp | 114 void PutInWorklist(unsigned RegIdx) { argument 115 if (WorklistMembers.test(RegIdx)) 117 WorklistMembers.set(RegIdx); 118 Worklist.push_back(RegIdx); 366 unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg); local 367 DefinedByCopy.set(RegIdx); 368 PutInWorklist(RegIdx); 499 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { 510 unsigned RegIdx = Worklist.front(); local 547 unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg); local [all...] |
H A D | SplitKit.h | 303 /// intervals. Given a pair (RegIdx, ParentVNI->id), Values contains: 305 /// 1. No entry - the value is not mapped to Edit.get(RegIdx). 307 /// Edit.get(RegIdx). Each value is represented by a minimal live range at 309 /// of RegIdx in RegAssign. 321 /// getLRCalc - Return the LRCalc to use for RegIdx. In spill mode, the 324 LiveRangeCalc &getLRCalc(unsigned RegIdx) { argument 325 return LRCalc[SpillMode != SM_Partition && RegIdx != 0]; 328 /// defValue - define a value in RegIdx from ParentVNI at Idx. 333 VNInfo *defValue(unsigned RegIdx, const VNInfo *ParentVNI, SlotIndex Idx); 335 /// forceRecompute - Force the live range of ParentVNI in RegIdx t [all...] |
H A D | SplitKit.cpp | 384 VNInfo *SplitEditor::defValue(unsigned RegIdx, argument 390 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); 397 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), 400 // This was the first time (RegIdx, ParentVNI) was mapped. 420 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI) { argument 422 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->id)]; 435 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); 441 VNInfo *SplitEditor::defFromParent(unsigned RegIdx, argument 448 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); 451 // so always begin RegIdx 680 unsigned RegIdx = AssignI.value(); local 931 unsigned RegIdx; local 947 DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx); local 1033 unsigned RegIdx = RegAssign.lookup(PHIVNI->def); local 1084 unsigned RegIdx = RegAssign.lookup(Idx); local 1148 unsigned RegIdx = RegAssign.lookup(ParentVNI->def); local [all...] |
H A D | LiveVariables.cpp | 85 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { argument 86 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) && 88 VirtRegInfo.grow(RegIdx); 89 return VirtRegInfo[RegIdx];
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | SplitKit.h | 268 /// intervals. Given a pair (RegIdx, ParentVNI->id), Values contains: 270 /// 1. No entry - the value is not mapped to Edit.get(RegIdx). 272 /// Edit.get(RegIdx). Each value is represented by a minimal live range at 274 /// of RegIdx in RegAssign. 286 /// getLRCalc - Return the LRCalc to use for RegIdx. In spill mode, the 289 LiveRangeCalc &getLRCalc(unsigned RegIdx) { argument 290 return LRCalc[SpillMode != SM_Partition && RegIdx != 0]; 293 /// defValue - define a value in RegIdx from ParentVNI at Idx. 298 VNInfo *defValue(unsigned RegIdx, const VNInfo *ParentVNI, SlotIndex Idx); 300 /// forceRecompute - Force the live range of ParentVNI in RegIdx t [all...] |
H A D | SplitKit.cpp | 345 VNInfo *SplitEditor::defValue(unsigned RegIdx, argument 351 LiveInterval *LI = Edit->get(RegIdx); 358 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), 361 // This was the first time (RegIdx, ParentVNI) was mapped. 381 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI) { argument 383 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->id)]; 396 Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI)); 401 VNInfo *SplitEditor::defFromParent(unsigned RegIdx, argument 408 LiveInterval *LI = Edit->get(RegIdx); 411 // so always begin RegIdx 638 unsigned RegIdx = AssignI.value(); local 816 unsigned RegIdx; local 832 DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx); local 922 unsigned RegIdx = RegAssign.lookup(PHIVNI->def); local 964 unsigned RegIdx = RegAssign.lookup(Idx); local 1030 unsigned RegIdx = RegAssign.lookup(ParentVNI->def); local [all...] |
H A D | LiveVariables.cpp | 81 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { argument 82 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) && 84 VirtRegInfo.grow(RegIdx); 85 return VirtRegInfo[RegIdx];
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/external/llvm/lib/Target/ARM/ |
H A D | ARMCallingConv.h | 210 unsigned RegIdx = State.getFirstUnallocated(RegList); local 215 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) 216 State.AllocateReg(RegList[RegIdx++]); 251 unsigned RegIdx = State.getFirstUnallocated(RegList); local 253 if (RegIdx >= RegList.size()) 256 It.convertToReg(State.AllocateReg(RegList[RegIdx++]));
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H A D | ARMISelLowering.cpp | 3247 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs); local 3248 if (RegIdx != array_lengthof(GPRArgRegs)) 3249 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
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/external/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 626 struct RegIdxOp RegIdx; member in union:__anon14415::MipsOperand::__anon14416 640 Op->RegIdx.Index = Index; 641 Op->RegIdx.RegInfo = RegInfo; 642 Op->RegIdx.Kind = RegKind; 652 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); 653 AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc); 655 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 661 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); 663 return RegIdx [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | LiveVariables.h | 274 VarInfo &getVarInfo(unsigned RegIdx);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelDAGToDAG.h | 34 unsigned getMSACtrlReg(const SDValue RegIdx) const;
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H A D | MipsSEISelDAGToDAG.cpp | 72 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const { 73 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) { 821 SDValue RegIdx = Node->getOperand(2); local 823 getMSACtrlReg(RegIdx), MVT::i32); 854 SDValue RegIdx = Node->getOperand(2); local 857 getMSACtrlReg(RegIdx), Value);
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | LiveVariables.h | 281 VarInfo &getVarInfo(unsigned RegIdx);
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/external/llvm/lib/Target/AMDGPU/InstPrinter/ |
H A D | AMDGPUInstPrinter.cpp | 236 unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1); local 275 RegIdx -= 112; // Trap temps start at offset 112. TODO: Get this from tablegen. 279 RegIdx -= 112; // Trap temps start at offset 112. TODO: Get this from tablegen. 286 O << RegIdx; local 290 O << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
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/external/llvm/lib/Target/AMDGPU/ |
H A D | SILowerControlFlow.cpp | 615 int RegIdx = BaseRegIdx + Offset; local 616 if (RegIdx < 0) { 617 Offset = RegIdx; 618 RegIdx = 0; 623 unsigned Reg = RC->getRegister(RegIdx);
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/external/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 2480 unsigned RegIdx = X86::sub_16bit; local 2481 ResultReg = fastEmitInst_extractsubreg(MVT::i16, ResultReg, true, RegIdx);
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 5745 unsigned RegIdx = 3; local 5752 RegIdx = 4; 5754 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() && 5756 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) || 5758 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
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