| /external/llvm/lib/Target/BPF/InstPrinter/ |
| H A D | BPFInstPrinter.cpp | 68 const MCOperand &RegOp = MI->getOperand(OpNo); local
77 assert(RegOp.isReg() && "Register operand not a register");
78 O << '(' << getRegisterName(RegOp.getReg()) << ')';
|
| /external/llvm/lib/Target/Lanai/InstPrinter/ |
| H A D | LanaiInstPrinter.cpp | 211 const MCOperand &RegOp) {
212 assert(RegOp.isReg() && "Register operand expected");
216 OS << "%" << LanaiInstPrinter::getRegisterName(RegOp.getReg());
237 const MCOperand &RegOp = MI->getOperand(OpNo); local
246 printMemoryBaseRegister(OS, AluCode, RegOp);
252 const MCOperand &RegOp = MI->getOperand(OpNo); local
256 assert(OffsetOp.isReg() && RegOp.isReg() && "Registers expected.");
262 OS << "%" << getRegisterName(RegOp.getReg());
273 const MCOperand &RegOp = MI->getOperand(OpNo); local
282 printMemoryBaseRegister(OS, AluCode, RegOp);
210 printMemoryBaseRegister(raw_ostream &OS, const unsigned AluCode, const MCOperand &RegOp) argument
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 394 /// Get all register state flags from machine operand \p RegOp.
395 inline unsigned getRegState(const MachineOperand &RegOp) { argument
396 assert(RegOp.isReg() && "Not a register operand");
397 return getDefRegState(RegOp.isDef()) |
398 getImplRegState(RegOp.isImplicit()) |
399 getKillRegState(RegOp.isKill()) |
400 getDeadRegState(RegOp.isDead()) |
401 getUndefRegState(RegOp.isUndef()) |
402 getInternalReadRegState(RegOp.isInternalRead()) |
403 getDebugRegState(RegOp
[all...] |
| /external/llvm/lib/Target/Lanai/ |
| H A D | LanaiAsmPrinter.cpp | 132 unsigned RegOp = OpNo + 1; local
133 if (RegOp >= MI->getNumOperands())
135 const MachineOperand &MO = MI->getOperand(RegOp);
|
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsAsmPrinter.cpp | 498 unsigned RegOp = OpNum; local
504 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
507 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
510 RegOp = OpNum + 1;
512 if (RegOp >= MI->getNumOperands())
514 const MachineOperand &MO = MI->getOperand(RegOp);
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfCompileUnit.cpp | 511 const MachineOperand RegOp = DVInsn->getOperand(0); local
514 MachineLocation Location(RegOp.getReg(),
517 } else if (RegOp.getReg())
518 addVariableAddress(DV, *VariableDie, MachineLocation(RegOp.getReg()));
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 44 struct RegOp { struct in struct:llvm::X86Operand
64 struct RegOp Reg;
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 149 unsigned RegOp, unsigned MemOp, unsigned Flags);
|
| H A D | X86MCInstLower.cpp | 260 unsigned RegOp = IsStore ? 0 : 5; local
262 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
272 unsigned Reg = Inst.getOperand(RegOp).getReg();
|
| H A D | X86InstrInfo.cpp | 65 // Used for RegOp->MemOp conversion.
73 // Do not insert the reverse map (MemOp -> RegOp) into the table.
77 // Do not insert the forward map (RegOp -> MemOp) into the table.
263 unsigned RegOp = OpTbl2Addr[i][0]; local
267 RegOp, MemOp,
373 unsigned RegOp = OpTbl0[i][0]; local
377 RegOp, MemOp, TB_INDEX_0 | Flags);
533 unsigned RegOp = OpTbl1[i][0]; local
537 RegOp, MemOp,
894 unsigned RegOp local
905 AddTableEntry(RegOp2MemOpTableType &R2MTable, MemOp2RegOpTableType &M2RTable, unsigned RegOp, unsigned MemOp, unsigned Flags) argument
[all...] |
| /external/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 165 uint16_t RegOp, uint16_t MemOp, uint16_t Flags);
|
| H A D | X86MCInstLower.cpp | 310 unsigned RegOp = IsStore ? 0 : 5; local
312 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
322 unsigned Reg = Inst.getOperand(RegOp).getReg();
|
| H A D | X86InstrInfo.cpp | 83 // Do not insert the reverse map (MemOp -> RegOp) into the table.
87 // Do not insert the forward map (RegOp -> MemOp) into the table.
96 // Used for RegOp->MemOp conversion.
107 uint16_t RegOp; member in struct:X86MemoryFoldTableEntry
289 Entry.RegOp, Entry.MemOp,
444 Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
881 Entry.RegOp, Entry.MemOp,
1754 Entry.RegOp, Entry.MemOp,
1991 Entry.RegOp, Entry.MemOp,
2040 Entry.RegOp, Entr
2047 AddTableEntry(RegOp2MemOpTableType &R2MTable, MemOp2RegOpTableType &M2RTable, uint16_t RegOp, uint16_t MemOp, uint16_t Flags) argument
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfCompileUnit.cpp | 1246 const MachineOperand RegOp = DVInsn->getOperand(0); local
1249 TRI->getFrameRegister(*Asm->MF) == RegOp.getReg()) {
1259 } else if (RegOp.getReg())
1261 MachineLocation(RegOp.getReg()));
|
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 86 struct RegOp { struct in class:__anon14505::SystemZOperand
113 RegOp Reg;
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 361 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1; local
362 if (RegOp >= MI->getNumOperands())
364 const MachineOperand &MO = MI->getOperand(RegOp);
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| H A D | LiveIntervalAnalysis.cpp | 943 unsigned RegOp = 0; local
956 assert(!RegOp &&
958 RegOp = MO.getReg();
963 return RegOp;
|
| /external/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 105 struct RegOp { struct in struct:llvm::__anon14393::LanaiOperand
122 struct RegOp Reg;
|
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 201 struct RegOp { struct in class:__anon14494::SparcOperand
218 struct RegOp Reg;
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 486 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1; local
487 if (RegOp >= MI->getNumOperands())
489 const MachineOperand &MO = MI->getOperand(RegOp);
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 177 struct RegOp { struct in class:__anon14183::AArch64Operand
252 struct RegOp Reg;
4000 AArch64Operand &RegOp = static_cast<AArch64Operand &>(*Operands[1]); local
4002 if (RegOp.isReg() && ImmOp.isFPImm() && ImmOp.getFPImm() == (unsigned)-1) {
4005 RegOp.getReg())
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGRRList.cpp | 1249 if (const auto *RegOp = dyn_cast<RegisterMaskSDNode>(Op.getNode()))
1250 return RegOp->getRegMask();
|
| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 145 struct RegOp { struct in class:__anon14213::AMDGPUOperand
156 RegOp Reg;
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 488 struct RegOp { struct in class:__anon14271::ARMOperand
572 struct RegOp Reg;
4763 unsigned RegOp = 4; local
4767 RegOp = 5;
4768 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
|