/external/vixl/src/aarch64/ |
H A D | operands-aarch64.cc | 321 // Extend modes SXTX and UXTX require a 64-bit register. 322 VIXL_ASSERT(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX))); 342 (((extend_ == UXTX) || (extend_ == SXTX)) && (shift_amount_ == 0))); 407 VIXL_ASSERT((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); 409 // SXTX extend mode requires a 64-bit offset register. 410 VIXL_ASSERT(regoffset.Is64Bits() || (extend != SXTX)); 468 VIXL_ASSERT((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX)); 469 VIXL_ASSERT((regoffset_.Is64Bits() || (extend_ != SXTX)));
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H A D | disasm-aarch64.cc | 165 const char *form = ((mode == UXTX) || (mode == SXTX)) ? "'Rds, 'Rns, 'Xm'Ext" 168 ((mode == UXTX) || (mode == SXTX)) ? "'Rns, 'Xm'Ext" : "'Rns, 'Wm'Ext";
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H A D | macro-assembler-aarch64.cc | 899 ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX))); 1812 ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX)));
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H A D | constants-aarch64.h | 293 SXTX = 7 enumerator in enum:vixl::aarch64::Extend
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H A D | simulator-aarch64.cc | 416 case SXTX: 1287 VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX));
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H A D | assembler-aarch64.cc | 4203 case SXTX: {
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/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64AddressingModes.h | 48 SXTX, enumerator in enum:llvm::AArch64_AM::ShiftExtendType 67 case AArch64_AM::SXTX: return "sxtx"; 134 case 7: return AArch64_AM::SXTX; 161 case AArch64_AM::SXTX: return 7; break;
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/external/vixl/test/aarch64/ |
H A D | test-api-aarch64.cc | 294 VIXL_CHECK(Operand(x6, SXTX).IsPlainRegister()); 306 VIXL_CHECK(!Operand(x6, SXTX, 2).IsPlainRegister());
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H A D | test-disasm-aarch64.cc | 439 COMPARE(adds(x27, x28, Operand(x29, SXTX)), "adds x27, x28, x29, sxtx"); 465 COMPARE(subs(x27, x28, Operand(x29, SXTX)), "subs x27, x28, x29, sxtx"); 1064 COMPARE(ldr(w18, MemOperand(x19, x20, SXTX)), "ldr w18, [x19, x20, sxtx]"); 1065 COMPARE(ldr(w21, MemOperand(x22, x23, SXTX, 2)), 1074 COMPARE(ldr(x18, MemOperand(x19, x20, SXTX)), "ldr x18, [x19, x20, sxtx]"); 1075 COMPARE(ldr(x21, MemOperand(x22, x23, SXTX, 3)), 1085 COMPARE(str(w18, MemOperand(x19, x20, SXTX)), "str w18, [x19, x20, sxtx]"); 1086 COMPARE(str(w21, MemOperand(x22, x23, SXTX, 2)), 1095 COMPARE(str(x18, MemOperand(x19, x20, SXTX)), "str x18, [x19, x20, sxtx]"); 1096 COMPARE(str(x21, MemOperand(x22, x23, SXTX, [all...] |
H A D | test-assembler-aarch64.cc | 745 __ Orr(x13, x0, Operand(x1, SXTX, 3)); 839 __ Orn(x13, x0, Operand(x1, SXTX, 3)); 906 __ And(x13, x0, Operand(x1, SXTX, 3)); 1044 __ Bic(x13, x0, Operand(x1, SXTX, 3)); 1168 __ Eor(x13, x0, Operand(x1, SXTX, 3)); 1235 __ Eon(x13, x0, Operand(x1, SXTX, 3)); 7714 __ Prfm(op, MemOperand(x0, input, SXTX)); 7715 __ Prfm(op, MemOperand(x0, input, SXTX, 3)); 8821 __ Adcs(x10, x0, Operand(x1, SXTX, 1));
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/external/v8/src/arm64/ |
H A D | assembler-arm64-inl.h | 351 // Extend modes SXTX and UXTX require a 64-bit register. 352 DCHECK(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX))); 466 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); 468 // SXTX extend mode requires a 64-bit offset register. 469 DCHECK(regoffset.Is64Bits() || (extend != SXTX)); 519 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX)); 520 DCHECK((regoffset_.Is64Bits() || (extend_ != SXTX)));
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H A D | disasm-arm64.cc | 144 const char *form = ((mode == UXTX) || (mode == SXTX)) ? 146 const char *form_cmp = ((mode == UXTX) || (mode == SXTX)) ?
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H A D | constants-arm64.h | 346 SXTX = 7 enumerator in enum:v8::internal::Extend
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H A D | simulator-arm64.cc | 996 case SXTX: 1615 DCHECK((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX));
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H A D | macro-assembler-arm64.cc | 147 ((operand.extend() != UXTX) && (operand.extend() != SXTX))); 549 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
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H A D | assembler-arm64.cc | 2507 case SXTX: {
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/external/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.h | 367 SXTX enumerator in enum:llvm::AArch64SE::ShiftExtSpecifiers
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/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 991 ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX || 999 // UXTX and SXTX require a 64-bit source register (the ExtendLSL64 class). 1001 return ET != AArch64_AM::UXTX && ET != AArch64_AM::SXTX; 1007 return (ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX || 1016 return (ET == AArch64_AM::LSL || ET == AArch64_AM::SXTX) && 1577 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; 1589 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; 2396 .Case("sxtx", AArch64_AM::SXTX)
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 1068 Addr.getExtendType() == AArch64_AM::SXTX;
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H A D | AArch64ISelDAGToDAG.cpp | 596 assert(Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX);
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