/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineShifts.cpp | 543 BinaryOperator *ShiftOp = dyn_cast<BinaryOperator>(Op0); local 544 if (ShiftOp && !ShiftOp->isShift()) 545 ShiftOp = nullptr; 547 if (ShiftOp && isa<ConstantInt>(ShiftOp->getOperand(1))) { 561 ConstantInt *ShiftAmt1C = cast<ConstantInt>(ShiftOp->getOperand(1)); 566 Value *X = ShiftOp->getOperand(0); 571 if (I.getOpcode() == ShiftOp->getOpcode()) { 588 ShiftOp [all...] |
/external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/ |
H A D | InstCombineShifts.cpp | 526 BinaryOperator *ShiftOp = dyn_cast<BinaryOperator>(Op0); local 527 if (ShiftOp && !ShiftOp->isShift()) 528 ShiftOp = 0; 530 if (ShiftOp && isa<ConstantInt>(ShiftOp->getOperand(1))) { 531 ConstantInt *ShiftAmt1C = cast<ConstantInt>(ShiftOp->getOperand(1)); 536 Value *X = ShiftOp->getOperand(0); 543 if (I.getOpcode() == ShiftOp->getOpcode()) { 559 ShiftOp [all...] |
/external/v8/src/arm/ |
H A D | constants-arm.h | 256 enum ShiftOp { enum in namespace:v8::internal 263 // Use a special code to make the distinction. The RRX ShiftOp is only used 588 inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); } 589 inline ShiftOp ShiftField() const { 590 return static_cast<ShiftOp>(BitField(6, 5));
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H A D | assembler-arm.h | 506 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm); 520 explicit Operand(Register rm, ShiftOp shift_op, Register rs); 546 ShiftOp shift_op() const { return shift_op_; } 551 ShiftOp shift_op_; 579 ShiftOp shift_op, int shift_imm, AddrMode am = Offset); 609 ShiftOp shift_op_;
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H A D | disasm-arm.cc | 193 ShiftOp shift = instr->ShiftField();
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H A D | assembler-arm.cc | 390 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) { 411 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) { 445 ShiftOp shift_op, int shift_imm, AddrMode am) {
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H A D | simulator-arm.cc | 1397 ShiftOp shift = instr->ShiftField();
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/external/swiftshader/third_party/subzero/src/ |
H A D | IceInstARM32.h | 114 Variable *Index, ShiftKind ShiftOp = kNoShift, 118 OperandARM32Mem(Func, Ty, Base, Index, ShiftOp, ShiftAmt, Mode); 123 ShiftKind getShiftOp() const { return ShiftOp; } 155 ShiftKind ShiftOp, uint16_t ShiftAmt, AddrMode Mode); 160 ShiftKind ShiftOp; member in class:Ice::ARM32::OperandARM32Mem 311 ShiftKind ShiftOp, Operand *ShiftAmt) { 313 OperandARM32FlexReg(Func, Ty, Reg, ShiftOp, ShiftAmt); 325 ShiftKind getShiftOp() const { return ShiftOp; } 330 OperandARM32FlexReg(Cfg *Func, Type Ty, Variable *Reg, ShiftKind ShiftOp, 334 ShiftKind ShiftOp; member in class:Ice::ARM32::OperandARM32FlexReg 310 create(Cfg *Func, Type Ty, Variable *Reg, ShiftKind ShiftOp, Operand *ShiftAmt) argument [all...] |
H A D | IceInstARM32.cpp | 328 ShiftOp(kNoShift), ShiftAmt(0), Mode(Mode) { 336 Variable *Index, ShiftKind ShiftOp, 339 ShiftOp(ShiftOp), ShiftAmt(ShiftAmt), Mode(Mode) { 476 ShiftKind ShiftOp, Operand *ShiftAmt) 477 : OperandARM32Flex(kFlexReg, Ty), Reg(Reg), ShiftOp(ShiftOp), 335 OperandARM32Mem(Cfg *Func, Type Ty, Variable *Base, Variable *Index, ShiftKind ShiftOp, uint16_t ShiftAmt, AddrMode Mode) argument 475 OperandARM32FlexReg(Cfg *Func, Type Ty, Variable *Reg, ShiftKind ShiftOp, Operand *ShiftAmt) argument
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 566 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); local 567 bool isASR = (ShiftOp & (1 << 5)) != 0; 568 unsigned Amt = ShiftOp & 0x1f;
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/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 694 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); 695 bool isASR = (ShiftOp & (1 << 5)) != 0; 696 unsigned Amt = ShiftOp & 0x1f;
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMCodeEmitter.cpp | 1452 unsigned ShiftOp = MI.getOperand(3).getImm(); 1453 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 2362 SDValue ShiftOp = N->getOperand(1); local 2367 if (ShiftOp.getValueType() != ShiftTy) 2368 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); 2370 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
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H A D | SelectionDAGBuilder.cpp | 2201 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT); 2210 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT), 2216 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT), 2221 DAG.getConstant(1, dl, VT), ShiftOp);
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/external/capstone/arch/ARM/ |
H A D | ARMInstPrinter.c | 1324 unsigned ShiftOp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); local 1325 bool isASR = (ShiftOp & (1 << 5)) != 0; 1326 unsigned Amt = ShiftOp & 0x1f;
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGBuilder.cpp | 1742 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), local 1751 ShiftOp, 1758 ShiftOp, 1764 DAG.getConstant(1, VT), ShiftOp);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 3228 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL; local 3273 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1)
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 28576 SDValue ShiftOp = Shift.getOperand(0); local [all...] |