Searched refs:ShiftOp (Results 1 - 18 of 18) sorted by relevance

/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineShifts.cpp543 BinaryOperator *ShiftOp = dyn_cast<BinaryOperator>(Op0); local
544 if (ShiftOp && !ShiftOp->isShift())
545 ShiftOp = nullptr;
547 if (ShiftOp && isa<ConstantInt>(ShiftOp->getOperand(1))) {
561 ConstantInt *ShiftAmt1C = cast<ConstantInt>(ShiftOp->getOperand(1));
566 Value *X = ShiftOp->getOperand(0);
571 if (I.getOpcode() == ShiftOp->getOpcode()) {
588 ShiftOp
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/external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/
H A DInstCombineShifts.cpp526 BinaryOperator *ShiftOp = dyn_cast<BinaryOperator>(Op0); local
527 if (ShiftOp && !ShiftOp->isShift())
528 ShiftOp = 0;
530 if (ShiftOp && isa<ConstantInt>(ShiftOp->getOperand(1))) {
531 ConstantInt *ShiftAmt1C = cast<ConstantInt>(ShiftOp->getOperand(1));
536 Value *X = ShiftOp->getOperand(0);
543 if (I.getOpcode() == ShiftOp->getOpcode()) {
559 ShiftOp
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/external/v8/src/arm/
H A Dconstants-arm.h256 enum ShiftOp { enum in namespace:v8::internal
263 // Use a special code to make the distinction. The RRX ShiftOp is only used
588 inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); }
589 inline ShiftOp ShiftField() const {
590 return static_cast<ShiftOp>(BitField(6, 5));
H A Dassembler-arm.h506 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm);
520 explicit Operand(Register rm, ShiftOp shift_op, Register rs);
546 ShiftOp shift_op() const { return shift_op_; }
551 ShiftOp shift_op_;
579 ShiftOp shift_op, int shift_imm, AddrMode am = Offset);
609 ShiftOp shift_op_;
H A Ddisasm-arm.cc193 ShiftOp shift = instr->ShiftField();
H A Dassembler-arm.cc390 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) {
411 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) {
445 ShiftOp shift_op, int shift_imm, AddrMode am) {
H A Dsimulator-arm.cc1397 ShiftOp shift = instr->ShiftField();
/external/swiftshader/third_party/subzero/src/
H A DIceInstARM32.h114 Variable *Index, ShiftKind ShiftOp = kNoShift,
118 OperandARM32Mem(Func, Ty, Base, Index, ShiftOp, ShiftAmt, Mode);
123 ShiftKind getShiftOp() const { return ShiftOp; }
155 ShiftKind ShiftOp, uint16_t ShiftAmt, AddrMode Mode);
160 ShiftKind ShiftOp; member in class:Ice::ARM32::OperandARM32Mem
311 ShiftKind ShiftOp, Operand *ShiftAmt) {
313 OperandARM32FlexReg(Func, Ty, Reg, ShiftOp, ShiftAmt);
325 ShiftKind getShiftOp() const { return ShiftOp; }
330 OperandARM32FlexReg(Cfg *Func, Type Ty, Variable *Reg, ShiftKind ShiftOp,
334 ShiftKind ShiftOp; member in class:Ice::ARM32::OperandARM32FlexReg
310 create(Cfg *Func, Type Ty, Variable *Reg, ShiftKind ShiftOp, Operand *ShiftAmt) argument
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H A DIceInstARM32.cpp328 ShiftOp(kNoShift), ShiftAmt(0), Mode(Mode) {
336 Variable *Index, ShiftKind ShiftOp,
339 ShiftOp(ShiftOp), ShiftAmt(ShiftAmt), Mode(Mode) {
476 ShiftKind ShiftOp, Operand *ShiftAmt)
477 : OperandARM32Flex(kFlexReg, Ty), Reg(Reg), ShiftOp(ShiftOp),
335 OperandARM32Mem(Cfg *Func, Type Ty, Variable *Base, Variable *Index, ShiftKind ShiftOp, uint16_t ShiftAmt, AddrMode Mode) argument
475 OperandARM32FlexReg(Cfg *Func, Type Ty, Variable *Reg, ShiftKind ShiftOp, Operand *ShiftAmt) argument
/external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp566 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); local
567 bool isASR = (ShiftOp & (1 << 5)) != 0;
568 unsigned Amt = ShiftOp & 0x1f;
/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp694 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
695 bool isASR = (ShiftOp & (1 << 5)) != 0;
696 unsigned Amt = ShiftOp & 0x1f;
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMCodeEmitter.cpp1452 unsigned ShiftOp = MI.getOperand(3).getImm();
1453 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp2362 SDValue ShiftOp = N->getOperand(1); local
2367 if (ShiftOp.getValueType() != ShiftTy)
2368 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
2370 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
H A DSelectionDAGBuilder.cpp2201 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2210 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2216 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2221 DAG.getConstant(1, dl, VT), ShiftOp);
/external/capstone/arch/ARM/
H A DARMInstPrinter.c1324 unsigned ShiftOp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); local
1325 bool isASR = (ShiftOp & (1 << 5)) != 0;
1326 unsigned Amt = ShiftOp & 0x1f;
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp1742 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), local
1751 ShiftOp,
1758 ShiftOp,
1764 DAG.getConstant(1, VT), ShiftOp);
/external/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp3228 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL; local
3273 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1)
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp28576 SDValue ShiftOp = Shift.getOperand(0); local
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