Searched refs:SrcOp (Results 1 - 21 of 21) sorted by relevance

/external/llvm/lib/Linker/
H A DIRMover.cpp1045 MDNode *SrcOp = SrcModFlags->getOperand(I); local
1047 mdconst::extract<ConstantInt>(SrcOp->getOperand(0));
1048 MDString *ID = cast<MDString>(SrcOp->getOperand(1));
1058 if (Requirements.insert(cast<MDNode>(SrcOp->getOperand(2)))) {
1059 DstModFlags->addOperand(SrcOp);
1066 Flags[ID] = std::make_pair(SrcOp, DstModFlags->getNumOperands());
1067 DstModFlags->addOperand(SrcOp);
1080 SrcOp->getOperand(2) != DstOp->getOperand(2))
1086 DstModFlags->setOperand(DstIndex, SrcOp);
1087 Flags[ID].first = SrcOp;
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonRDFOpt.cpp123 const MachineOperand &SrcOp = MI->getOperand(1); local
125 { SrcOp.getReg(), SrcOp.getSubReg() });
H A DHexagonFrameLowering.cpp2108 MachineOperand &SrcOp = SI->getOperand(2); local
2110 HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(),
2111 SrcOp.getSubReg() };
2112 auto *RC = getRegClass({SrcOp.getReg(), SrcOp.getSubReg()});
2125 .addOperand(SrcOp);
2132 if (unsigned SR = SrcOp.getSubReg())
2133 SrcOp.setReg(HRI.getSubReg(FoundR, SR));
2135 SrcOp.setReg(FoundR);
2136 SrcOp
[all...]
H A DHexagonExpandCondsets.cpp249 MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
607 /// Generate a conditional transfer, copying the value SrcOp to the
611 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, argument
615 MachineInstr *MI = SrcOp.getParent();
625 unsigned Opc = getCondTfrOpcode(SrcOp, PredSense);
630 .addOperand(SrcOp);
/external/swiftshader/third_party/LLVM/utils/TableGen/
H A DCodeGenInstruction.cpp237 std::pair<unsigned,unsigned> SrcOp = local
239 if (SrcOp > DestOp)
243 unsigned FlatOpNo = Ops.getFlattenedOperandNumber(SrcOp);
/external/llvm/utils/TableGen/
H A DCodeGenInstruction.cpp244 std::pair<unsigned,unsigned> SrcOp = Ops.ParseOperandName(SrcOpName, false); local
245 if (SrcOp > DestOp) {
246 std::swap(SrcOp, DestOp);
250 unsigned FlatOpNo = Ops.getFlattenedOperandNumber(SrcOp);
/external/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp1467 const MachineOperand &SrcOp = MI->getOperand(SrcIdx); local
1474 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask));
1489 const MachineOperand &SrcOp = MI->getOperand(1); local
1496 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask));
1511 const MachineOperand &SrcOp = MI->getOperand(1); local
1518 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask));
H A DX86ISelLowering.cpp5470 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, unsigned NumBits, argument
5476 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5480 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5483 static SDValue LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, const SDLoc &dl, argument
5489 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
17037 SDValue SrcOp, uint64_t ShiftAmt,
17043 return SrcOp;
17056 // Fold this packed vector shift into a build vector if SrcOp is a
17057 // vector of Constants or UNDEFs, and SrcOp valuetyp
17036 getTargetVShiftByConstNode(unsigned Opc, const SDLoc &dl, MVT VT, SDValue SrcOp, uint64_t ShiftAmt, SelectionDAG &DAG) argument
17113 getTargetVShiftNode(unsigned Opc, const SDLoc &dl, MVT VT, SDValue SrcOp, SDValue ShAmt, SelectionDAG &DAG) argument
[all...]
/external/swiftshader/third_party/LLVM/lib/Analysis/
H A DInstructionSimplify.cpp1613 Value *SrcOp = LI->getOperand(0); local
1614 Type *SrcTy = SrcOp->getType();
1623 if (Value *V = SimplifyICmpInst(Pred, SrcOp,
1630 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0),
1643 SrcOp, RI->getOperand(0), TD, DT,
1659 SrcOp, Trunc, TD, DT, MaxRecurse-1))
1703 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0),
1718 if (Value *V = SimplifyICmpInst(Pred, SrcOp, Trunc, TD, DT,
1752 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SLT, SrcOp,
1761 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SGE, SrcOp,
[all...]
/external/llvm/tools/llvm-c-test/
H A Decho.cpp429 LLVMValueRef SrcOp = LLVMGetOperand(Src, 0); local
430 LLVMBasicBlockRef SrcBB = LLVMValueAsBasicBlock(SrcOp);
/external/llvm/lib/Analysis/
H A DInstructionSimplify.cpp2452 Value *SrcOp = LI->getOperand(0); local
2453 Type *SrcTy = SrcOp->getType();
2462 if (Value *V = SimplifyICmpInst(Pred, SrcOp,
2469 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0),
2482 SrcOp, RI->getOperand(0), Q,
2498 SrcOp, Trunc, Q, MaxRecurse-1))
2541 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0),
2556 if (Value *V = SimplifyICmpInst(Pred, SrcOp, Trunc, Q, MaxRecurse-1))
2588 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SLT, SrcOp,
2597 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SGE, SrcOp,
[all...]
/external/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp861 const MachineOperand &SrcOp = MI.getOperand(1); local
863 assert(!SrcOp.isFPImm());
864 if (SrcOp.isImm()) {
865 APInt Imm(64, SrcOp.getImm());
873 assert(SrcOp.isReg());
875 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
878 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86ISelLowering.h791 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
H A DX86ISelLowering.cpp4883 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, argument
4889 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4891 DAG.getNode(Opc, dl, ShVT, SrcOp,
4893 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4897 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, argument
4903 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5887 SDValue SrcOp, SelectionDAG &DAG,
5891 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5892 LD = dyn_cast<LoadSDNode>(SrcOp);
5886 getVZextMovL(EVT VT, EVT OpVT, SDValue SrcOp, SelectionDAG &DAG, const X86Subtarget *Subtarget, DebugLoc dl) argument
[all...]
/external/llvm/lib/Transforms/Vectorize/
H A DLoopVectorize.cpp2628 for (Value *SrcOp : Instr->operands()) {
2630 if (SrcOp == OldInduction) {
2631 Params.push_back(getVectorValue(SrcOp));
2636 auto *SrcInst = dyn_cast<Instruction>(SrcOp);
2647 Scalars.append(UF, SrcOp);
6229 for (Value *SrcOp : Instr->operands()) {
6231 if (SrcOp == OldInduction) {
6232 Params.push_back(getVectorValue(SrcOp));
6237 Instruction *SrcInst = dyn_cast<Instruction>(SrcOp);
6248 Scalars.append(UF, SrcOp);
[all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp131 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
1664 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1667 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1671 SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
1679 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1690 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1694 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp133 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
2022 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
2025 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
2031 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
2039 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
2050 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
2054 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
/external/llvm/lib/CodeGen/
H A DMachineScheduler.cpp1599 const MachineOperand &SrcOp = Copy->getOperand(1); local
1600 unsigned SrcReg = SrcOp.getReg();
1601 if (!TargetRegisterInfo::isVirtualRegister(SrcReg) || !SrcOp.readsReg())
/external/swiftshader/third_party/subzero/src/
H A DIceTargetLoweringX86BaseImpl.h5435 Operand *SrcOp = VarAssign->getSrc(0);
5436 assert(SrcOp);
5437 if (auto *SrcVar = llvm::dyn_cast<Variable>(SrcOp)) {
5444 } else if (auto *Const = llvm::dyn_cast<ConstantInteger32>(SrcOp)) {
5451 } else if (auto *AddReloc = llvm::dyn_cast<ConstantRelocatable>(SrcOp)) {
H A DIceTargetLoweringMIPS32.cpp5250 Operand *SrcOp = VarAssign->getSrc(0);
5252 if (auto *SrcVar = llvm::dyn_cast<Variable>(SrcOp)) {
5258 } else if (auto *Const = llvm::dyn_cast<ConstantInteger32>(SrcOp)) {
H A DIceTargetLoweringARM32.cpp5525 Operand *SrcOp = VarAssign->getSrc(0);
5527 if (auto *SrcVar = llvm::dyn_cast<Variable>(SrcOp)) {
5533 } else if (auto *Const = llvm::dyn_cast<ConstantInteger32>(SrcOp)) {

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