/external/vixl/src/aarch64/ |
H A D | operands-aarch64.cc | 339 // __ Add(w0, w0, Operand(w1, UXTW)); 341 // __ Add(x0, x0, Operand(w1, UXTW)); 368 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_); 407 VIXL_ASSERT((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); 468 VIXL_ASSERT((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
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H A D | constants-aarch64.h | 288 UXTW = 2, enumerator in enum:vixl::aarch64::Extend
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H A D | simulator-aarch64.cc | 394 case UXTW: 1287 VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX));
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H A D | assembler-aarch64.cc | 4194 case UXTW:
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/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64AddressingModes.h | 42 UXTW, enumerator in enum:llvm::AArch64_AM::ShiftExtendType 62 case AArch64_AM::UXTW: return "uxtw"; 129 case 2: return AArch64_AM::UXTW; 156 case AArch64_AM::UXTW: return 2; break;
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/external/v8/src/compiler/arm64/ |
H A D | code-generator-arm64.cc | 438 __ Ldr(result, MemOperand(buffer, offset, UXTW)); \ 450 __ asm_instr(result, MemOperand(buffer, offset, UXTW)); \ 462 __ asm_instr(result, MemOperand(buffer, offset, UXTW)); \ 474 __ Str(value, MemOperand(buffer, offset, UXTW)); \ 486 __ asm_instr(value, MemOperand(buffer, offset, UXTW)); \ 498 __ asm_instr(value, MemOperand(buffer, offset, UXTW)); \ 1800 __ Add(temp, temp, Operand(input, UXTW, 2));
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/external/vixl/test/aarch64/ |
H A D | test-disasm-aarch64.cc | 433 COMPARE(adds(x9, x10, Operand(x11, UXTW, 3)), "adds x9, x10, w11, uxtw #3"); 445 COMPARE(add(wsp, wsp, Operand(w4, UXTW, 2)), "add wsp, wsp, w4, lsl #2"); 459 COMPARE(subs(x9, x10, Operand(x11, UXTW, 3)), "subs x9, x10, w11, uxtw #3"); 471 COMPARE(sub(wsp, wsp, Operand(w4, UXTW, 2)), "sub wsp, wsp, w4, lsl #2"); 1057 COMPARE(ldr(w0, MemOperand(x1, w2, UXTW)), "ldr w0, [x1, w2, uxtw]"); 1058 COMPARE(ldr(w3, MemOperand(x4, w5, UXTW, 2)), "ldr w3, [x4, w5, uxtw #2]"); 1067 COMPARE(ldr(x0, MemOperand(x1, w2, UXTW)), "ldr x0, [x1, w2, uxtw]"); 1068 COMPARE(ldr(x3, MemOperand(x4, w5, UXTW, 3)), "ldr x3, [x4, w5, uxtw #3]"); 1078 COMPARE(str(w0, MemOperand(x1, w2, UXTW)), "str w0, [x1, w2, uxtw]"); 1079 COMPARE(str(w3, MemOperand(x4, w5, UXTW, [all...] |
H A D | test-api-aarch64.cc | 315 // UXTW and SXTW could be treated as plain registers in 32-bit contexts, but 317 VIXL_CHECK(!Operand(w15, UXTW).IsPlainRegister());
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H A D | test-simulator-aarch64.cc | 229 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, n_index_shift)); 351 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); 355 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); 486 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); 490 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); 494 __ Ldr(fa, MemOperand(inputs_base, index_a, UXTW, index_shift)); 633 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); 637 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); 770 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); 897 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, n_index_shif [all...] |
H A D | test-assembler-aarch64.cc | 432 __ Mvn(x14, Operand(w2, UXTW, 4)); 607 __ Mov(x27, Operand(w13, UXTW, 4)); 668 __ Mov(x29, Operand(x12, UXTW, 1)); 740 __ Orr(w8, w0, Operand(w1, UXTW, 2)); 834 __ Orn(w8, w0, Operand(w1, UXTW, 2)); 901 __ And(w8, w0, Operand(w1, UXTW, 2)); 1039 __ Bic(w8, w0, Operand(w1, UXTW, 2)); 1163 __ Eor(w8, w0, Operand(w1, UXTW, 2)); 1230 __ Eon(w8, w0, Operand(w1, UXTW, 2)); 3088 __ Ldr(h3, MemOperand(x17, x18, UXTW, [all...] |
/external/v8/src/arm64/ |
H A D | assembler-arm64-inl.h | 383 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_); 466 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); 519 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
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H A D | constants-arm64.h | 341 UXTW = 2, enumerator in enum:v8::internal::Extend
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H A D | code-stubs-arm64.cc | 1537 __ Add(x2, start, Operand(w10, UXTW)); 1542 __ Add(x3, x2, Operand(w10, UXTW));
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H A D | simulator-arm64.cc | 983 case UXTW: 1615 DCHECK((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX));
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H A D | assembler-arm64.cc | 2502 case UXTW: ubfm(rd, rn_, non_shift_bits, high_bit); break;
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H A D | macro-assembler-arm64.cc | 1070 PushPreamble(Operand(count, UXTW, WhichPowerOf2(src.SizeInBytes())));
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/external/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.h | 361 UXTW, enumerator in enum:llvm::AArch64SE::ShiftExtSpecifiers
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/external/v8/src/regexp/arm64/ |
H A D | regexp-macro-assembler-arm64.cc | 191 __ Add(x10, code_pointer(), Operand(w10, UXTW)); 581 __ Ldrb(w11, MemOperand(x11, w10, UXTW)); 662 __ Ldrb(w10, MemOperand(x10, current_character(), UXTW)); 675 __ Ldrb(w10, MemOperand(x10, current_character(), UXTW));
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 670 Addr.setExtendType(AArch64_AM::UXTW); 694 Addr.setExtendType(AArch64_AM::UXTW); 754 Addr.setExtendType(AArch64_AM::UXTW); 791 Addr.setExtendType(AArch64_AM::UXTW); 813 Addr.setExtendType(AArch64_AM::UXTW); 991 Addr.getExtendType() == AArch64_AM::UXTW ) 1002 if (Addr.getExtendType() == AArch64_AM::UXTW) 1770 if (Addr.getExtendType() == AArch64_AM::UXTW || 2037 if (Addr.getExtendType() == AArch64_AM::UXTW ||
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H A D | AArch64ISelDAGToDAG.cpp | 393 return AArch64_AM::UXTW; 411 return AArch64_AM::UXTW; 547 /// Instructions that accept extend modifiers like UXTW expect the register
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/external/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.cpp | 1102 // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at 1104 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { 1110 ExtType == AArch64_AM::UXTW) ) {
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/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 990 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW || 1025 return (ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW) && 1561 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTW; 2391 .Case("uxtw", AArch64_AM::UXTW)
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/external/v8/src/crankshaft/arm64/ |
H A D | lithium-codegen-arm64.cc | 1337 __ Ldr(result, MemOperand(arguments, result, UXTW, kPointerSizeLog2)); 1339 __ Ldr(result, MemOperand(arguments, length, UXTW, kPointerSizeLog2)); 1346 __ Ldr(result, MemOperand(arguments, result, UXTW, kPointerSizeLog2));
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