Searched refs:VReg (Results 1 - 25 of 79) sorted by relevance

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/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMachineFunctionInfo.h62 void stackifyVReg(unsigned VReg) { argument
63 if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size())
64 VRegStackified.resize(TargetRegisterInfo::virtReg2Index(VReg) + 1);
65 VRegStackified.set(TargetRegisterInfo::virtReg2Index(VReg));
67 bool isVRegStackified(unsigned VReg) const {
68 if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size())
70 return VRegStackified.test(TargetRegisterInfo::virtReg2Index(VReg));
74 void setWAReg(unsigned VReg, unsigned WAReg) { argument
76 assert(TargetRegisterInfo::virtReg2Index(VReg) < WARegs.size());
77 WARegs[TargetRegisterInfo::virtReg2Index(VReg)]
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H A DWebAssemblyRegNumbering.cpp77 DEBUG(dbgs() << "Arg VReg " << MI.getOperand(0).getReg() << " -> WAReg "
95 unsigned VReg = TargetRegisterInfo::index2VirtReg(VRegIdx); local
97 if (MRI.use_empty(VReg))
100 if (MFI.isVRegStackified(VReg)) {
101 DEBUG(dbgs() << "VReg " << VReg << " -> WAReg "
103 MFI.setWAReg(VReg, INT32_MIN | NumStackRegs++);
106 if (MFI.getWAReg(VReg) == WebAssemblyFunctionInfo::UnusedReg) {
107 DEBUG(dbgs() << "VReg " << VReg << "
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H A DWebAssemblyReplacePhysRegs.cpp84 unsigned VReg = WebAssembly::NoRegister; local
88 if (VReg == WebAssembly::NoRegister)
89 VReg = MRI.createVirtualRegister(RC);
90 MO.setReg(VReg);
H A DWebAssemblyRegColoring.cpp62 // Compute the total spill weight for VReg.
65 unsigned VReg) {
67 for (MachineOperand &MO : MRI->reg_nodbg_operands(VReg))
99 unsigned VReg = TargetRegisterInfo::index2VirtReg(i); local
100 if (MFI.isVRegStackified(VReg))
103 if (MRI->use_empty(VReg))
106 LiveInterval *LI = &Liveness->getInterval(VReg);
108 LI->weight = computeWeight(MRI, MBFI, VReg);
63 computeWeight(const MachineRegisterInfo *MRI, const MachineBlockFrequencyInfo *MBFI, unsigned VReg) argument
/external/llvm/lib/Target/AArch64/
H A DAArch64CallLowering.h29 unsigned VReg) const override;
H A DAArch64CallLowering.cpp33 const Value *Val, unsigned VReg) const {
37 assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
38 if (VReg) {
46 MIRBuilder.buildInstr(TargetOpcode::COPY, ResReg, VReg);
/external/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp33 const Value *Val, unsigned VReg) const {
H A DAMDGPUCallLowering.h29 unsigned VReg) const override;
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DLiveIntervalUnion.h124 Query(LiveInterval *VReg, LiveIntervalUnion *LIU): argument
125 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
140 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) { argument
141 assert(VReg && LIU && "Invalid arguments");
142 if (UserTag == UTag && VirtReg == VReg &&
149 VirtReg = VReg;
167 bool isSeenInterference(LiveInterval *VReg) const;
H A DLiveIntervalUnion.cpp150 LiveInterval *VReg = LiveUnionI.value(); local
151 if (VReg != RecentReg && !isSeenInterference(VReg)) {
152 RecentReg = VReg;
153 InterferingVRegs.push_back(VReg);
H A DMachineFunction.cpp393 unsigned VReg = MRI.getLiveInVirtReg(PReg); local
394 if (VReg) {
395 assert(MRI.getRegClass(VReg) == RC && "Register class mismatch!");
396 return VReg;
398 VReg = MRI.createVirtualRegister(RC);
399 MRI.addLiveIn(PReg, VReg);
400 return VReg;
/external/llvm/include/llvm/CodeGen/
H A DLiveIntervalUnion.h125 Query(LiveInterval *VReg, LiveIntervalUnion *LIU): argument
126 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
141 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) { argument
142 assert(VReg && LIU && "Invalid arguments");
143 if (UserTag == UTag && VirtReg == VReg &&
150 VirtReg = VReg;
168 bool isSeenInterference(LiveInterval *VReg) const;
H A DRegAllocPBQP.h155 void setNodeIdForVReg(unsigned VReg, GraphBase::NodeId NId) { argument
156 VRegToNodeId[VReg] = NId;
159 GraphBase::NodeId getNodeIdForVReg(unsigned VReg) const {
160 auto VRegItr = VRegToNodeId.find(VReg);
166 void eraseNodeIdForVReg(unsigned VReg) { argument
167 VRegToNodeId.erase(VReg);
196 VReg(0)
206 OptUnsafeEdges(new unsigned[NumOpts]), VReg(Other.VReg),
222 OptUnsafeEdges(std::move(Other.OptUnsafeEdges)), VReg(Othe
261 setVReg(unsigned VReg) argument
321 unsigned VReg; member in class:llvm::PBQP::RegAlloc::NodeMetadata
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H A DMachineRegisterInfo.h194 bool shouldTrackSubRegLiveness(unsigned VReg) const {
195 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Must pass a VReg");
196 return shouldTrackSubRegLiveness(*getRegClass(VReg));
648 /// Get the size in bits of \p VReg or 0 if VReg is not a generic
650 unsigned getSize(unsigned VReg) const;
652 /// Set the size in bits of \p VReg to \p Size.
655 void setSize(unsigned VReg, unsigned Size);
670 void setRegAllocationHint(unsigned VReg, unsigne argument
678 setSimpleHint(unsigned VReg, unsigned PrefReg) argument
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H A DScheduleDAGInstrs.h40 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU) argument
41 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
52 VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask, argument
54 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {}
/external/dexmaker/dexmaker-mockito-inline/src/main/jni/dexmakerjvmtiagent/
H A Dagent.cc387 VReg* v0 = c.Alloc<VReg>(0);
388 VReg* v1 = c.Alloc<VReg>(1);
389 VReg* v2 = c.Alloc<VReg>(2);
390 VReg* thiz = c.Alloc<VReg>(thisReg);
402 addInstr(c, fi, OP_MOVE_OBJECT_FROM16, {v0, c.Alloc<VReg>(thisReg + 1)});
410 addInstr(c, fi, OP_MOVE_OBJECT_16, {c.Alloc<VReg>(thisRe
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/external/llvm/include/llvm/CodeGen/GlobalISel/
H A DCallLowering.h45 /// by \p Val, into the specified virtual register \p VReg.
50 unsigned VReg) const {
/external/llvm/lib/CodeGen/
H A DLiveRangeEdit.cpp35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); local
37 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
39 LiveInterval &LI = LIS.createEmptyInterval(VReg);
44 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); local
46 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
48 return VReg;
383 unsigned VReg = LI->reg; local
385 TheDelegate->LRE_WillShrinkVirtReg(VReg);
395 if (VReg == RegsBeingSpilled[i]) {
410 unsigned Original = VRM ? VRM->getOriginal(VReg)
426 MRI_NoteNewVirtualRegister(unsigned VReg) argument
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H A DLiveIntervalUnion.cpp150 LiveInterval *VReg = LiveUnionI.value(); local
151 if (VReg != RecentReg && !isSeenInterference(VReg)) {
152 RecentReg = VReg;
153 InterferingVRegs.push_back(VReg);
H A DRegAllocPBQP.cpp138 /// \brief Spill the given VReg.
139 void spillVReg(unsigned VReg, SmallVectorImpl<unsigned> &NewIntervals,
305 unsigned VReg = G.getNodeMetadata(NId).getVReg(); variable
306 LiveInterval &LI = LIS.getInterval(VReg);
573 unsigned VReg = Worklist.back(); local
576 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
577 LiveInterval &VRegLI = LIS.getInterval(VReg);
614 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
628 G.getNodeMetadata(NId).setVReg(VReg);
631 G.getMetadata().setNodeIdForVReg(VReg, NI
635 spillVReg(unsigned VReg, SmallVectorImpl<unsigned> &NewIntervals, MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM, Spiller &VRegSpiller) argument
681 unsigned VReg = G.getNodeMetadata(NId).getVReg(); local
834 unsigned VReg = G.getNodeMetadata(NId).getVReg(); local
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H A DMachineRegisterInfo.cpp111 MachineRegisterInfo::getSize(unsigned VReg) const {
112 VRegToSizeMap::const_iterator SizeIt = getVRegToSize().find(VReg);
116 void MachineRegisterInfo::setSize(unsigned VReg, unsigned Size) { argument
117 getVRegToSize()[VReg] = Size;
377 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
379 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
381 if (I->second == VReg)
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp251 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); local
254 if (!VReg) {
256 VReg = MRI->createVirtualRegister(RC);
259 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
260 return VReg;
282 unsigned VReg = getVR(Op, VRBaseMap); local
283 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
291 // shrink VReg's register class within reason. For example, if VReg == GR32
292 // and II requires a GR32_NOSP, just constrain VReg t
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp289 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); local
292 if (!VReg) {
295 VReg = MRI->createVirtualRegister(RC);
298 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
299 return VReg;
322 unsigned VReg = getVR(Op, VRBaseMap); local
330 // shrink VReg's register class within reason. For example, if VReg == GR32
331 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
336 assert((!DstRC || TargetRegisterInfo::isVirtualRegister(VReg))
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/external/llvm/lib/CodeGen/MIRParser/
H A DMIRParser.cpp368 for (const auto &VReg : YamlMF.VirtualRegisters) {
370 if (StringRef(VReg.Class.Value).equals("_")) {
376 const auto *RC = getRegClass(MF, VReg.Class.Value);
380 const auto *RegBank = getRegBank(MF, VReg.Class.Value);
383 VReg.Class.SourceRange.Start,
385 VReg.Class.Value + "'");
391 if (!PFS.VirtualRegisterSlots.insert(std::make_pair(VReg.ID.Value, Reg))
393 return error(VReg.ID.SourceRange.Start,
395 Twine(VReg.ID.Value) + "'");
396 if (!VReg
410 unsigned VReg = 0; local
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/external/llvm/lib/CodeGen/GlobalISel/
H A DIRTranslator.cpp47 unsigned VReg = MRI->createGenericVirtualRegister(Size); local
48 ValReg = VReg;

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