| /external/llvm/lib/Target/X86/ |
| H A D | X86FixupSetCC.cpp | 163 unsigned ZeroReg = MRI->createVirtualRegister(RC); local
168 ZeroReg);
174 .addReg(ZeroReg)
|
| H A D | X86FrameLowering.cpp | 509 // ZeroReg = 0
512 // FinalReg = !Flags.Ovf ? TestReg : ZeroReg
552 ZeroReg = InProlog ? (unsigned)X86::RCX
598 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg)
599 .addReg(ZeroReg, RegState::Undef)
600 .addReg(ZeroReg, RegState::Undef);
607 .addReg(ZeroReg);
|
| /external/swiftshader/third_party/subzero/src/ |
| H A D | IceTargetLoweringX8664.cpp | 350 Variable *ZeroReg = RebasePtr; local
369 assert(ZeroReg == Base || AbsoluteAddress || isAssignedToRspOrRbp(Base));
371 // If Mem is an absolute address, no need to update ZeroReg (which is
373 ZeroReg = Base;
385 ZeroReg = Base;
400 // If the Index is not shifted, and it is a Valid Base, and the ZeroReg is
401 // still RebasePtr, then we do ZeroReg = Index, and hopefully prevent the
404 if (Shift == 0 && isAssignedToRspOrRbp(Index) && ZeroReg == RebasePtr) {
405 ZeroReg = Index;
432 if (Base != nullptr && Base != ZeroReg)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| H A D | MipsInstrInfo.cpp | 106 unsigned Opc = 0, ZeroReg = 0; local
110 Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
138 Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
158 if (ZeroReg)
159 MIB.addReg(ZeroReg);
|
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 89 unsigned DstReg = 0, ZeroReg = 0; local
96 ZeroReg = Mips::ZERO;
101 ZeroReg = Mips::ZERO_64;
107 // Replace uses with ZeroReg.
121 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
124 MO.setReg(ZeroReg);
|
| H A D | MipsSEInstrInfo.cpp | 83 unsigned Opc = 0, ZeroReg = 0; local
91 Opc = Mips::OR, ZeroReg = Mips::ZERO;
147 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
178 if (ZeroReg)
179 MIB.addReg(ZeroReg);
|
| H A D | MipsAsmPrinter.cpp | 122 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; local
123 TmpInst0.addOperand(MCOperand::createReg(ZeroReg));
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 2851 unsigned CombineOpc, unsigned ZeroReg = 0,
2870 if (MI->getOperand(3).getReg() != ZeroReg)
2880 unsigned MulOpc, unsigned ZeroReg) {
2881 return canCombine(MBB, MO, MulOpc, ZeroReg, true);
3438 unsigned BitSize, OrrOpc, ZeroReg; local
3443 ZeroReg = AArch64::WZR;
3450 ZeroReg = AArch64::XZR;
3466 .addReg(ZeroReg)
3482 unsigned SubOpc, ZeroReg; local
3486 ZeroReg
2879 canCombineWithMUL(MachineBasicBlock &MBB, MachineOperand &MO, unsigned MulOpc, unsigned ZeroReg) argument
3530 unsigned BitSize, OrrOpc, ZeroReg; local
[all...] |
| H A D | AArch64ExpandPseudoInsts.cpp | 57 unsigned ExtendImm, unsigned ZeroReg,
599 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg,
634 BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg)
|
| H A D | AArch64FastISel.cpp | 345 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; local
348 ResultReg).addReg(ZeroReg, getKillRegState(true));
4800 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; local
4803 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, /*IsKill=*/true,
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 2169 unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg(); local
2189 SrcReg = ZeroReg;
2211 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI);
2236 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI);
2265 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI);
3033 unsigned ZeroReg; local
3037 ZeroReg = Mips::ZERO_64;
3040 ZeroReg = Mips::ZERO;
3051 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
3068 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg,
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1263 unsigned ZeroReg; variable
1266 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1268 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1273 UseMI.getOperand(UseIdx).setReg(ZeroReg); variable
|
| H A D | PPCISelLowering.cpp | 8518 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; local
8579 if (ptrA != ZeroReg) {
8609 .addReg(ZeroReg).addReg(PtrReg);
8620 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
9271 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; local
9304 if (ptrA != ZeroReg) {
9341 .addReg(ZeroReg).addReg(PtrReg);
9357 .addReg(ZeroReg).addReg(PtrReg);
9366 .addReg(ZeroReg).addReg(PtrReg);
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 4724 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; local
4788 if (ptrA != ZeroReg) {
4818 .addReg(ZeroReg).addReg(PtrReg);
4829 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
5087 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; local
5120 if (ptrA != ZeroReg) {
5157 .addReg(ZeroReg).addReg(PtrReg);
5173 .addReg(ZeroReg).addReg(PtrReg);
5182 .addReg(ZeroReg).addReg(PtrReg);
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1277 unsigned ZeroReg = TargetMaterializeConstant(Zero); local
1279 .addReg(ZeroReg).addImm(1)
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1486 unsigned ZeroReg = fastMaterializeConstant(Zero); local
1489 .addReg(ZeroReg).addImm(1)
|