1//===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the PowerPC implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCInstrInfo.h" 15#include "MCTargetDesc/PPCPredicates.h" 16#include "PPC.h" 17#include "PPCHazardRecognizers.h" 18#include "PPCInstrBuilder.h" 19#include "PPCMachineFunctionInfo.h" 20#include "PPCTargetMachine.h" 21#include "llvm/ADT/STLExtras.h" 22#include "llvm/ADT/Statistic.h" 23#include "llvm/CodeGen/LiveIntervalAnalysis.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunctionPass.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineMemOperand.h" 28#include "llvm/CodeGen/MachineRegisterInfo.h" 29#include "llvm/CodeGen/PseudoSourceValue.h" 30#include "llvm/CodeGen/ScheduleDAG.h" 31#include "llvm/CodeGen/SlotIndexes.h" 32#include "llvm/CodeGen/StackMaps.h" 33#include "llvm/MC/MCAsmInfo.h" 34#include "llvm/MC/MCInst.h" 35#include "llvm/Support/CommandLine.h" 36#include "llvm/Support/Debug.h" 37#include "llvm/Support/ErrorHandling.h" 38#include "llvm/Support/TargetRegistry.h" 39#include "llvm/Support/raw_ostream.h" 40 41using namespace llvm; 42 43#define DEBUG_TYPE "ppc-instr-info" 44 45#define GET_INSTRMAP_INFO 46#define GET_INSTRINFO_CTOR_DTOR 47#include "PPCGenInstrInfo.inc" 48 49static cl:: 50opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, 51 cl::desc("Disable analysis for CTR loops")); 52 53static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt", 54cl::desc("Disable compare instruction optimization"), cl::Hidden); 55 56static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", 57cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), 58cl::Hidden); 59 60static cl::opt<bool> 61UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, 62 cl::desc("Use the old (incorrect) instruction latency calculation")); 63 64// Pin the vtable to this file. 65void PPCInstrInfo::anchor() {} 66 67PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI) 68 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 69 Subtarget(STI), RI(STI.getTargetMachine()) {} 70 71/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for 72/// this target when scheduling the DAG. 73ScheduleHazardRecognizer * 74PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 75 const ScheduleDAG *DAG) const { 76 unsigned Directive = 77 static_cast<const PPCSubtarget *>(STI)->getDarwinDirective(); 78 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 || 79 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) { 80 const InstrItineraryData *II = 81 static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData(); 82 return new ScoreboardHazardRecognizer(II, DAG); 83 } 84 85 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG); 86} 87 88/// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer 89/// to use for this target when scheduling the DAG. 90ScheduleHazardRecognizer * 91PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 92 const ScheduleDAG *DAG) const { 93 unsigned Directive = 94 DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective(); 95 96 // FIXME: Leaving this as-is until we have POWER9 scheduling info 97 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8) 98 return new PPCDispatchGroupSBHazardRecognizer(II, DAG); 99 100 // Most subtargets use a PPC970 recognizer. 101 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 && 102 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) { 103 assert(DAG->TII && "No InstrInfo?"); 104 105 return new PPCHazardRecognizer970(*DAG); 106 } 107 108 return new ScoreboardHazardRecognizer(II, DAG); 109} 110 111unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 112 const MachineInstr &MI, 113 unsigned *PredCost) const { 114 if (!ItinData || UseOldLatencyCalc) 115 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost); 116 117 // The default implementation of getInstrLatency calls getStageLatency, but 118 // getStageLatency does not do the right thing for us. While we have 119 // itinerary, most cores are fully pipelined, and so the itineraries only 120 // express the first part of the pipeline, not every stage. Instead, we need 121 // to use the listed output operand cycle number (using operand 0 here, which 122 // is an output). 123 124 unsigned Latency = 1; 125 unsigned DefClass = MI.getDesc().getSchedClass(); 126 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 127 const MachineOperand &MO = MI.getOperand(i); 128 if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) 129 continue; 130 131 int Cycle = ItinData->getOperandCycle(DefClass, i); 132 if (Cycle < 0) 133 continue; 134 135 Latency = std::max(Latency, (unsigned) Cycle); 136 } 137 138 return Latency; 139} 140 141int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 142 const MachineInstr &DefMI, unsigned DefIdx, 143 const MachineInstr &UseMI, 144 unsigned UseIdx) const { 145 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, 146 UseMI, UseIdx); 147 148 if (!DefMI.getParent()) 149 return Latency; 150 151 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); 152 unsigned Reg = DefMO.getReg(); 153 154 bool IsRegCR; 155 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 156 const MachineRegisterInfo *MRI = 157 &DefMI.getParent()->getParent()->getRegInfo(); 158 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || 159 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); 160 } else { 161 IsRegCR = PPC::CRRCRegClass.contains(Reg) || 162 PPC::CRBITRCRegClass.contains(Reg); 163 } 164 165 if (UseMI.isBranch() && IsRegCR) { 166 if (Latency < 0) 167 Latency = getInstrLatency(ItinData, DefMI); 168 169 // On some cores, there is an additional delay between writing to a condition 170 // register, and using it from a branch. 171 unsigned Directive = Subtarget.getDarwinDirective(); 172 switch (Directive) { 173 default: break; 174 case PPC::DIR_7400: 175 case PPC::DIR_750: 176 case PPC::DIR_970: 177 case PPC::DIR_E5500: 178 case PPC::DIR_PWR4: 179 case PPC::DIR_PWR5: 180 case PPC::DIR_PWR5X: 181 case PPC::DIR_PWR6: 182 case PPC::DIR_PWR6X: 183 case PPC::DIR_PWR7: 184 case PPC::DIR_PWR8: 185 // FIXME: Is this needed for POWER9? 186 Latency += 2; 187 break; 188 } 189 } 190 191 return Latency; 192} 193 194// This function does not list all associative and commutative operations, but 195// only those worth feeding through the machine combiner in an attempt to 196// reduce the critical path. Mostly, this means floating-point operations, 197// because they have high latencies (compared to other operations, such and 198// and/or, which are also associative and commutative, but have low latencies). 199bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const { 200 switch (Inst.getOpcode()) { 201 // FP Add: 202 case PPC::FADD: 203 case PPC::FADDS: 204 // FP Multiply: 205 case PPC::FMUL: 206 case PPC::FMULS: 207 // Altivec Add: 208 case PPC::VADDFP: 209 // VSX Add: 210 case PPC::XSADDDP: 211 case PPC::XVADDDP: 212 case PPC::XVADDSP: 213 case PPC::XSADDSP: 214 // VSX Multiply: 215 case PPC::XSMULDP: 216 case PPC::XVMULDP: 217 case PPC::XVMULSP: 218 case PPC::XSMULSP: 219 // QPX Add: 220 case PPC::QVFADD: 221 case PPC::QVFADDS: 222 case PPC::QVFADDSs: 223 // QPX Multiply: 224 case PPC::QVFMUL: 225 case PPC::QVFMULS: 226 case PPC::QVFMULSs: 227 return true; 228 default: 229 return false; 230 } 231} 232 233bool PPCInstrInfo::getMachineCombinerPatterns( 234 MachineInstr &Root, 235 SmallVectorImpl<MachineCombinerPattern> &Patterns) const { 236 // Using the machine combiner in this way is potentially expensive, so 237 // restrict to when aggressive optimizations are desired. 238 if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOpt::Aggressive) 239 return false; 240 241 // FP reassociation is only legal when we don't need strict IEEE semantics. 242 if (!Root.getParent()->getParent()->getTarget().Options.UnsafeFPMath) 243 return false; 244 245 return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns); 246} 247 248// Detect 32 -> 64-bit extensions where we may reuse the low sub-register. 249bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 250 unsigned &SrcReg, unsigned &DstReg, 251 unsigned &SubIdx) const { 252 switch (MI.getOpcode()) { 253 default: return false; 254 case PPC::EXTSW: 255 case PPC::EXTSW_32_64: 256 SrcReg = MI.getOperand(1).getReg(); 257 DstReg = MI.getOperand(0).getReg(); 258 SubIdx = PPC::sub_32; 259 return true; 260 } 261} 262 263unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, 264 int &FrameIndex) const { 265 // Note: This list must be kept consistent with LoadRegFromStackSlot. 266 switch (MI.getOpcode()) { 267 default: break; 268 case PPC::LD: 269 case PPC::LWZ: 270 case PPC::LFS: 271 case PPC::LFD: 272 case PPC::RESTORE_CR: 273 case PPC::RESTORE_CRBIT: 274 case PPC::LVX: 275 case PPC::LXVD2X: 276 case PPC::QVLFDX: 277 case PPC::QVLFSXs: 278 case PPC::QVLFDXb: 279 case PPC::RESTORE_VRSAVE: 280 // Check for the operands added by addFrameReference (the immediate is the 281 // offset which defaults to 0). 282 if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() && 283 MI.getOperand(2).isFI()) { 284 FrameIndex = MI.getOperand(2).getIndex(); 285 return MI.getOperand(0).getReg(); 286 } 287 break; 288 } 289 return 0; 290} 291 292unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr &MI, 293 int &FrameIndex) const { 294 // Note: This list must be kept consistent with StoreRegToStackSlot. 295 switch (MI.getOpcode()) { 296 default: break; 297 case PPC::STD: 298 case PPC::STW: 299 case PPC::STFS: 300 case PPC::STFD: 301 case PPC::SPILL_CR: 302 case PPC::SPILL_CRBIT: 303 case PPC::STVX: 304 case PPC::STXVD2X: 305 case PPC::QVSTFDX: 306 case PPC::QVSTFSXs: 307 case PPC::QVSTFDXb: 308 case PPC::SPILL_VRSAVE: 309 // Check for the operands added by addFrameReference (the immediate is the 310 // offset which defaults to 0). 311 if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() && 312 MI.getOperand(2).isFI()) { 313 FrameIndex = MI.getOperand(2).getIndex(); 314 return MI.getOperand(0).getReg(); 315 } 316 break; 317 } 318 return 0; 319} 320 321MachineInstr *PPCInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, 322 unsigned OpIdx1, 323 unsigned OpIdx2) const { 324 MachineFunction &MF = *MI.getParent()->getParent(); 325 326 // Normal instructions can be commuted the obvious way. 327 if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo) 328 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2); 329 // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a 330 // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because 331 // changing the relative order of the mask operands might change what happens 332 // to the high-bits of the mask (and, thus, the result). 333 334 // Cannot commute if it has a non-zero rotate count. 335 if (MI.getOperand(3).getImm() != 0) 336 return nullptr; 337 338 // If we have a zero rotate count, we have: 339 // M = mask(MB,ME) 340 // Op0 = (Op1 & ~M) | (Op2 & M) 341 // Change this to: 342 // M = mask((ME+1)&31, (MB-1)&31) 343 // Op0 = (Op2 & ~M) | (Op1 & M) 344 345 // Swap op1/op2 346 assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) && 347 "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo."); 348 unsigned Reg0 = MI.getOperand(0).getReg(); 349 unsigned Reg1 = MI.getOperand(1).getReg(); 350 unsigned Reg2 = MI.getOperand(2).getReg(); 351 unsigned SubReg1 = MI.getOperand(1).getSubReg(); 352 unsigned SubReg2 = MI.getOperand(2).getSubReg(); 353 bool Reg1IsKill = MI.getOperand(1).isKill(); 354 bool Reg2IsKill = MI.getOperand(2).isKill(); 355 bool ChangeReg0 = false; 356 // If machine instrs are no longer in two-address forms, update 357 // destination register as well. 358 if (Reg0 == Reg1) { 359 // Must be two address instruction! 360 assert(MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && 361 "Expecting a two-address instruction!"); 362 assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch"); 363 Reg2IsKill = false; 364 ChangeReg0 = true; 365 } 366 367 // Masks. 368 unsigned MB = MI.getOperand(4).getImm(); 369 unsigned ME = MI.getOperand(5).getImm(); 370 371 // We can't commute a trivial mask (there is no way to represent an all-zero 372 // mask). 373 if (MB == 0 && ME == 31) 374 return nullptr; 375 376 if (NewMI) { 377 // Create a new instruction. 378 unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); 379 bool Reg0IsDead = MI.getOperand(0).isDead(); 380 return BuildMI(MF, MI.getDebugLoc(), MI.getDesc()) 381 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) 382 .addReg(Reg2, getKillRegState(Reg2IsKill)) 383 .addReg(Reg1, getKillRegState(Reg1IsKill)) 384 .addImm((ME + 1) & 31) 385 .addImm((MB - 1) & 31); 386 } 387 388 if (ChangeReg0) { 389 MI.getOperand(0).setReg(Reg2); 390 MI.getOperand(0).setSubReg(SubReg2); 391 } 392 MI.getOperand(2).setReg(Reg1); 393 MI.getOperand(1).setReg(Reg2); 394 MI.getOperand(2).setSubReg(SubReg1); 395 MI.getOperand(1).setSubReg(SubReg2); 396 MI.getOperand(2).setIsKill(Reg1IsKill); 397 MI.getOperand(1).setIsKill(Reg2IsKill); 398 399 // Swap the mask around. 400 MI.getOperand(4).setImm((ME + 1) & 31); 401 MI.getOperand(5).setImm((MB - 1) & 31); 402 return &MI; 403} 404 405bool PPCInstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, 406 unsigned &SrcOpIdx2) const { 407 // For VSX A-Type FMA instructions, it is the first two operands that can be 408 // commuted, however, because the non-encoded tied input operand is listed 409 // first, the operands to swap are actually the second and third. 410 411 int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode()); 412 if (AltOpc == -1) 413 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2); 414 415 // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1 416 // and SrcOpIdx2. 417 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3); 418} 419 420void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, 421 MachineBasicBlock::iterator MI) const { 422 // This function is used for scheduling, and the nop wanted here is the type 423 // that terminates dispatch groups on the POWER cores. 424 unsigned Directive = Subtarget.getDarwinDirective(); 425 unsigned Opcode; 426 switch (Directive) { 427 default: Opcode = PPC::NOP; break; 428 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break; 429 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break; 430 case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */ 431 // FIXME: Update when POWER9 scheduling model is ready. 432 case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break; 433 } 434 435 DebugLoc DL; 436 BuildMI(MBB, MI, DL, get(Opcode)); 437} 438 439/// getNoopForMachoTarget - Return the noop instruction to use for a noop. 440void PPCInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { 441 NopInst.setOpcode(PPC::NOP); 442} 443 444// Branch analysis. 445// Note: If the condition register is set to CTR or CTR8 then this is a 446// BDNZ (imm == 1) or BDZ (imm == 0) branch. 447bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB, 448 MachineBasicBlock *&TBB, 449 MachineBasicBlock *&FBB, 450 SmallVectorImpl<MachineOperand> &Cond, 451 bool AllowModify) const { 452 bool isPPC64 = Subtarget.isPPC64(); 453 454 // If the block has no terminators, it just falls into the block after it. 455 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); 456 if (I == MBB.end()) 457 return false; 458 459 if (!isUnpredicatedTerminator(*I)) 460 return false; 461 462 // Get the last instruction in the block. 463 MachineInstr *LastInst = I; 464 465 // If there is only one terminator instruction, process it. 466 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) { 467 if (LastInst->getOpcode() == PPC::B) { 468 if (!LastInst->getOperand(0).isMBB()) 469 return true; 470 TBB = LastInst->getOperand(0).getMBB(); 471 return false; 472 } else if (LastInst->getOpcode() == PPC::BCC) { 473 if (!LastInst->getOperand(2).isMBB()) 474 return true; 475 // Block ends with fall-through condbranch. 476 TBB = LastInst->getOperand(2).getMBB(); 477 Cond.push_back(LastInst->getOperand(0)); 478 Cond.push_back(LastInst->getOperand(1)); 479 return false; 480 } else if (LastInst->getOpcode() == PPC::BC) { 481 if (!LastInst->getOperand(1).isMBB()) 482 return true; 483 // Block ends with fall-through condbranch. 484 TBB = LastInst->getOperand(1).getMBB(); 485 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); 486 Cond.push_back(LastInst->getOperand(0)); 487 return false; 488 } else if (LastInst->getOpcode() == PPC::BCn) { 489 if (!LastInst->getOperand(1).isMBB()) 490 return true; 491 // Block ends with fall-through condbranch. 492 TBB = LastInst->getOperand(1).getMBB(); 493 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); 494 Cond.push_back(LastInst->getOperand(0)); 495 return false; 496 } else if (LastInst->getOpcode() == PPC::BDNZ8 || 497 LastInst->getOpcode() == PPC::BDNZ) { 498 if (!LastInst->getOperand(0).isMBB()) 499 return true; 500 if (DisableCTRLoopAnal) 501 return true; 502 TBB = LastInst->getOperand(0).getMBB(); 503 Cond.push_back(MachineOperand::CreateImm(1)); 504 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 505 true)); 506 return false; 507 } else if (LastInst->getOpcode() == PPC::BDZ8 || 508 LastInst->getOpcode() == PPC::BDZ) { 509 if (!LastInst->getOperand(0).isMBB()) 510 return true; 511 if (DisableCTRLoopAnal) 512 return true; 513 TBB = LastInst->getOperand(0).getMBB(); 514 Cond.push_back(MachineOperand::CreateImm(0)); 515 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 516 true)); 517 return false; 518 } 519 520 // Otherwise, don't know what this is. 521 return true; 522 } 523 524 // Get the instruction before it if it's a terminator. 525 MachineInstr *SecondLastInst = I; 526 527 // If there are three terminators, we don't know what sort of block this is. 528 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I)) 529 return true; 530 531 // If the block ends with PPC::B and PPC:BCC, handle it. 532 if (SecondLastInst->getOpcode() == PPC::BCC && 533 LastInst->getOpcode() == PPC::B) { 534 if (!SecondLastInst->getOperand(2).isMBB() || 535 !LastInst->getOperand(0).isMBB()) 536 return true; 537 TBB = SecondLastInst->getOperand(2).getMBB(); 538 Cond.push_back(SecondLastInst->getOperand(0)); 539 Cond.push_back(SecondLastInst->getOperand(1)); 540 FBB = LastInst->getOperand(0).getMBB(); 541 return false; 542 } else if (SecondLastInst->getOpcode() == PPC::BC && 543 LastInst->getOpcode() == PPC::B) { 544 if (!SecondLastInst->getOperand(1).isMBB() || 545 !LastInst->getOperand(0).isMBB()) 546 return true; 547 TBB = SecondLastInst->getOperand(1).getMBB(); 548 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); 549 Cond.push_back(SecondLastInst->getOperand(0)); 550 FBB = LastInst->getOperand(0).getMBB(); 551 return false; 552 } else if (SecondLastInst->getOpcode() == PPC::BCn && 553 LastInst->getOpcode() == PPC::B) { 554 if (!SecondLastInst->getOperand(1).isMBB() || 555 !LastInst->getOperand(0).isMBB()) 556 return true; 557 TBB = SecondLastInst->getOperand(1).getMBB(); 558 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); 559 Cond.push_back(SecondLastInst->getOperand(0)); 560 FBB = LastInst->getOperand(0).getMBB(); 561 return false; 562 } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 || 563 SecondLastInst->getOpcode() == PPC::BDNZ) && 564 LastInst->getOpcode() == PPC::B) { 565 if (!SecondLastInst->getOperand(0).isMBB() || 566 !LastInst->getOperand(0).isMBB()) 567 return true; 568 if (DisableCTRLoopAnal) 569 return true; 570 TBB = SecondLastInst->getOperand(0).getMBB(); 571 Cond.push_back(MachineOperand::CreateImm(1)); 572 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 573 true)); 574 FBB = LastInst->getOperand(0).getMBB(); 575 return false; 576 } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 || 577 SecondLastInst->getOpcode() == PPC::BDZ) && 578 LastInst->getOpcode() == PPC::B) { 579 if (!SecondLastInst->getOperand(0).isMBB() || 580 !LastInst->getOperand(0).isMBB()) 581 return true; 582 if (DisableCTRLoopAnal) 583 return true; 584 TBB = SecondLastInst->getOperand(0).getMBB(); 585 Cond.push_back(MachineOperand::CreateImm(0)); 586 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 587 true)); 588 FBB = LastInst->getOperand(0).getMBB(); 589 return false; 590 } 591 592 // If the block ends with two PPC:Bs, handle it. The second one is not 593 // executed, so remove it. 594 if (SecondLastInst->getOpcode() == PPC::B && 595 LastInst->getOpcode() == PPC::B) { 596 if (!SecondLastInst->getOperand(0).isMBB()) 597 return true; 598 TBB = SecondLastInst->getOperand(0).getMBB(); 599 I = LastInst; 600 if (AllowModify) 601 I->eraseFromParent(); 602 return false; 603 } 604 605 // Otherwise, can't handle this. 606 return true; 607} 608 609unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 610 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); 611 if (I == MBB.end()) 612 return 0; 613 614 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC && 615 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn && 616 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && 617 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) 618 return 0; 619 620 // Remove the branch. 621 I->eraseFromParent(); 622 623 I = MBB.end(); 624 625 if (I == MBB.begin()) return 1; 626 --I; 627 if (I->getOpcode() != PPC::BCC && 628 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn && 629 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && 630 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) 631 return 1; 632 633 // Remove the branch. 634 I->eraseFromParent(); 635 return 2; 636} 637 638unsigned PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, 639 MachineBasicBlock *TBB, 640 MachineBasicBlock *FBB, 641 ArrayRef<MachineOperand> Cond, 642 const DebugLoc &DL) const { 643 // Shouldn't be a fall through. 644 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 645 assert((Cond.size() == 2 || Cond.size() == 0) && 646 "PPC branch conditions have two components!"); 647 648 bool isPPC64 = Subtarget.isPPC64(); 649 650 // One-way branch. 651 if (!FBB) { 652 if (Cond.empty()) // Unconditional branch 653 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); 654 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) 655 BuildMI(&MBB, DL, get(Cond[0].getImm() ? 656 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : 657 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); 658 else if (Cond[0].getImm() == PPC::PRED_BIT_SET) 659 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB); 660 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET) 661 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB); 662 else // Conditional branch 663 BuildMI(&MBB, DL, get(PPC::BCC)) 664 .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB); 665 return 1; 666 } 667 668 // Two-way Conditional Branch. 669 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) 670 BuildMI(&MBB, DL, get(Cond[0].getImm() ? 671 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : 672 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); 673 else if (Cond[0].getImm() == PPC::PRED_BIT_SET) 674 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB); 675 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET) 676 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB); 677 else 678 BuildMI(&MBB, DL, get(PPC::BCC)) 679 .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB); 680 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); 681 return 2; 682} 683 684// Select analysis. 685bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB, 686 ArrayRef<MachineOperand> Cond, 687 unsigned TrueReg, unsigned FalseReg, 688 int &CondCycles, int &TrueCycles, int &FalseCycles) const { 689 if (!Subtarget.hasISEL()) 690 return false; 691 692 if (Cond.size() != 2) 693 return false; 694 695 // If this is really a bdnz-like condition, then it cannot be turned into a 696 // select. 697 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) 698 return false; 699 700 // Check register classes. 701 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 702 const TargetRegisterClass *RC = 703 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 704 if (!RC) 705 return false; 706 707 // isel is for regular integer GPRs only. 708 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && 709 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && 710 !PPC::G8RCRegClass.hasSubClassEq(RC) && 711 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) 712 return false; 713 714 // FIXME: These numbers are for the A2, how well they work for other cores is 715 // an open question. On the A2, the isel instruction has a 2-cycle latency 716 // but single-cycle throughput. These numbers are used in combination with 717 // the MispredictPenalty setting from the active SchedMachineModel. 718 CondCycles = 1; 719 TrueCycles = 1; 720 FalseCycles = 1; 721 722 return true; 723} 724 725void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB, 726 MachineBasicBlock::iterator MI, 727 const DebugLoc &dl, unsigned DestReg, 728 ArrayRef<MachineOperand> Cond, unsigned TrueReg, 729 unsigned FalseReg) const { 730 assert(Cond.size() == 2 && 731 "PPC branch conditions have two components!"); 732 733 assert(Subtarget.hasISEL() && 734 "Cannot insert select on target without ISEL support"); 735 736 // Get the register classes. 737 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 738 const TargetRegisterClass *RC = 739 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 740 assert(RC && "TrueReg and FalseReg must have overlapping register classes"); 741 742 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) || 743 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC); 744 assert((Is64Bit || 745 PPC::GPRCRegClass.hasSubClassEq(RC) || 746 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && 747 "isel is for regular integer GPRs only"); 748 749 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL; 750 auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm()); 751 752 unsigned SubIdx = 0; 753 bool SwapOps = false; 754 switch (SelectPred) { 755 case PPC::PRED_EQ: 756 case PPC::PRED_EQ_MINUS: 757 case PPC::PRED_EQ_PLUS: 758 SubIdx = PPC::sub_eq; SwapOps = false; break; 759 case PPC::PRED_NE: 760 case PPC::PRED_NE_MINUS: 761 case PPC::PRED_NE_PLUS: 762 SubIdx = PPC::sub_eq; SwapOps = true; break; 763 case PPC::PRED_LT: 764 case PPC::PRED_LT_MINUS: 765 case PPC::PRED_LT_PLUS: 766 SubIdx = PPC::sub_lt; SwapOps = false; break; 767 case PPC::PRED_GE: 768 case PPC::PRED_GE_MINUS: 769 case PPC::PRED_GE_PLUS: 770 SubIdx = PPC::sub_lt; SwapOps = true; break; 771 case PPC::PRED_GT: 772 case PPC::PRED_GT_MINUS: 773 case PPC::PRED_GT_PLUS: 774 SubIdx = PPC::sub_gt; SwapOps = false; break; 775 case PPC::PRED_LE: 776 case PPC::PRED_LE_MINUS: 777 case PPC::PRED_LE_PLUS: 778 SubIdx = PPC::sub_gt; SwapOps = true; break; 779 case PPC::PRED_UN: 780 case PPC::PRED_UN_MINUS: 781 case PPC::PRED_UN_PLUS: 782 SubIdx = PPC::sub_un; SwapOps = false; break; 783 case PPC::PRED_NU: 784 case PPC::PRED_NU_MINUS: 785 case PPC::PRED_NU_PLUS: 786 SubIdx = PPC::sub_un; SwapOps = true; break; 787 case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break; 788 case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break; 789 } 790 791 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, 792 SecondReg = SwapOps ? TrueReg : FalseReg; 793 794 // The first input register of isel cannot be r0. If it is a member 795 // of a register class that can be r0, then copy it first (the 796 // register allocator should eliminate the copy). 797 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || 798 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { 799 const TargetRegisterClass *FirstRC = 800 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? 801 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass; 802 unsigned OldFirstReg = FirstReg; 803 FirstReg = MRI.createVirtualRegister(FirstRC); 804 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg) 805 .addReg(OldFirstReg); 806 } 807 808 BuildMI(MBB, MI, dl, get(OpCode), DestReg) 809 .addReg(FirstReg).addReg(SecondReg) 810 .addReg(Cond[1].getReg(), 0, SubIdx); 811} 812 813static unsigned getCRBitValue(unsigned CRBit) { 814 unsigned Ret = 4; 815 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT || 816 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT || 817 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT || 818 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT) 819 Ret = 3; 820 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT || 821 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT || 822 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT || 823 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT) 824 Ret = 2; 825 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ || 826 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ || 827 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ || 828 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ) 829 Ret = 1; 830 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN || 831 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN || 832 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN || 833 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN) 834 Ret = 0; 835 836 assert(Ret != 4 && "Invalid CR bit register"); 837 return Ret; 838} 839 840void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 841 MachineBasicBlock::iterator I, 842 const DebugLoc &DL, unsigned DestReg, 843 unsigned SrcReg, bool KillSrc) const { 844 // We can end up with self copies and similar things as a result of VSX copy 845 // legalization. Promote them here. 846 const TargetRegisterInfo *TRI = &getRegisterInfo(); 847 if (PPC::F8RCRegClass.contains(DestReg) && 848 PPC::VSRCRegClass.contains(SrcReg)) { 849 unsigned SuperReg = 850 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass); 851 852 if (VSXSelfCopyCrash && SrcReg == SuperReg) 853 llvm_unreachable("nop VSX copy"); 854 855 DestReg = SuperReg; 856 } else if (PPC::VRRCRegClass.contains(DestReg) && 857 PPC::VSRCRegClass.contains(SrcReg)) { 858 unsigned SuperReg = 859 TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass); 860 861 if (VSXSelfCopyCrash && SrcReg == SuperReg) 862 llvm_unreachable("nop VSX copy"); 863 864 DestReg = SuperReg; 865 } else if (PPC::F8RCRegClass.contains(SrcReg) && 866 PPC::VSRCRegClass.contains(DestReg)) { 867 unsigned SuperReg = 868 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass); 869 870 if (VSXSelfCopyCrash && DestReg == SuperReg) 871 llvm_unreachable("nop VSX copy"); 872 873 SrcReg = SuperReg; 874 } else if (PPC::VRRCRegClass.contains(SrcReg) && 875 PPC::VSRCRegClass.contains(DestReg)) { 876 unsigned SuperReg = 877 TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass); 878 879 if (VSXSelfCopyCrash && DestReg == SuperReg) 880 llvm_unreachable("nop VSX copy"); 881 882 SrcReg = SuperReg; 883 } 884 885 // Different class register copy 886 if (PPC::CRBITRCRegClass.contains(SrcReg) && 887 PPC::GPRCRegClass.contains(DestReg)) { 888 unsigned CRReg = getCRFromCRBit(SrcReg); 889 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg); 890 getKillRegState(KillSrc); 891 // Rotate the CR bit in the CR fields to be the least significant bit and 892 // then mask with 0x1 (MB = ME = 31). 893 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg) 894 .addReg(DestReg, RegState::Kill) 895 .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg))) 896 .addImm(31) 897 .addImm(31); 898 return; 899 } else if (PPC::CRRCRegClass.contains(SrcReg) && 900 PPC::G8RCRegClass.contains(DestReg)) { 901 BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg); 902 getKillRegState(KillSrc); 903 return; 904 } else if (PPC::CRRCRegClass.contains(SrcReg) && 905 PPC::GPRCRegClass.contains(DestReg)) { 906 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg); 907 getKillRegState(KillSrc); 908 return; 909 } 910 911 unsigned Opc; 912 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) 913 Opc = PPC::OR; 914 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) 915 Opc = PPC::OR8; 916 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) 917 Opc = PPC::FMR; 918 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) 919 Opc = PPC::MCRF; 920 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) 921 Opc = PPC::VOR; 922 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg)) 923 // There are two different ways this can be done: 924 // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only 925 // issue in VSU pipeline 0. 926 // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but 927 // can go to either pipeline. 928 // We'll always use xxlor here, because in practically all cases where 929 // copies are generated, they are close enough to some use that the 930 // lower-latency form is preferable. 931 Opc = PPC::XXLOR; 932 else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) || 933 PPC::VSSRCRegClass.contains(DestReg, SrcReg)) 934 Opc = PPC::XXLORf; 935 else if (PPC::QFRCRegClass.contains(DestReg, SrcReg)) 936 Opc = PPC::QVFMR; 937 else if (PPC::QSRCRegClass.contains(DestReg, SrcReg)) 938 Opc = PPC::QVFMRs; 939 else if (PPC::QBRCRegClass.contains(DestReg, SrcReg)) 940 Opc = PPC::QVFMRb; 941 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) 942 Opc = PPC::CROR; 943 else 944 llvm_unreachable("Impossible reg-to-reg copy"); 945 946 const MCInstrDesc &MCID = get(Opc); 947 if (MCID.getNumOperands() == 3) 948 BuildMI(MBB, I, DL, MCID, DestReg) 949 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); 950 else 951 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); 952} 953 954// This function returns true if a CR spill is necessary and false otherwise. 955bool 956PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, 957 unsigned SrcReg, bool isKill, 958 int FrameIdx, 959 const TargetRegisterClass *RC, 960 SmallVectorImpl<MachineInstr*> &NewMIs, 961 bool &NonRI, bool &SpillsVRS) const{ 962 // Note: If additional store instructions are added here, 963 // update isStoreToStackSlot. 964 965 DebugLoc DL; 966 if (PPC::GPRCRegClass.hasSubClassEq(RC) || 967 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { 968 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 969 .addReg(SrcReg, 970 getKillRegState(isKill)), 971 FrameIdx)); 972 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) || 973 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) { 974 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 975 .addReg(SrcReg, 976 getKillRegState(isKill)), 977 FrameIdx)); 978 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { 979 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) 980 .addReg(SrcReg, 981 getKillRegState(isKill)), 982 FrameIdx)); 983 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { 984 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) 985 .addReg(SrcReg, 986 getKillRegState(isKill)), 987 FrameIdx)); 988 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { 989 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) 990 .addReg(SrcReg, 991 getKillRegState(isKill)), 992 FrameIdx)); 993 return true; 994 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { 995 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT)) 996 .addReg(SrcReg, 997 getKillRegState(isKill)), 998 FrameIdx)); 999 return true; 1000 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { 1001 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX)) 1002 .addReg(SrcReg, 1003 getKillRegState(isKill)), 1004 FrameIdx)); 1005 NonRI = true; 1006 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) { 1007 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXVD2X)) 1008 .addReg(SrcReg, 1009 getKillRegState(isKill)), 1010 FrameIdx)); 1011 NonRI = true; 1012 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) { 1013 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSDX)) 1014 .addReg(SrcReg, 1015 getKillRegState(isKill)), 1016 FrameIdx)); 1017 NonRI = true; 1018 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) { 1019 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSSPX)) 1020 .addReg(SrcReg, 1021 getKillRegState(isKill)), 1022 FrameIdx)); 1023 NonRI = true; 1024 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) { 1025 assert(Subtarget.isDarwin() && 1026 "VRSAVE only needs spill/restore on Darwin"); 1027 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE)) 1028 .addReg(SrcReg, 1029 getKillRegState(isKill)), 1030 FrameIdx)); 1031 SpillsVRS = true; 1032 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) { 1033 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDX)) 1034 .addReg(SrcReg, 1035 getKillRegState(isKill)), 1036 FrameIdx)); 1037 NonRI = true; 1038 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) { 1039 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFSXs)) 1040 .addReg(SrcReg, 1041 getKillRegState(isKill)), 1042 FrameIdx)); 1043 NonRI = true; 1044 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) { 1045 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDXb)) 1046 .addReg(SrcReg, 1047 getKillRegState(isKill)), 1048 FrameIdx)); 1049 NonRI = true; 1050 } else { 1051 llvm_unreachable("Unknown regclass!"); 1052 } 1053 1054 return false; 1055} 1056 1057void 1058PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 1059 MachineBasicBlock::iterator MI, 1060 unsigned SrcReg, bool isKill, int FrameIdx, 1061 const TargetRegisterClass *RC, 1062 const TargetRegisterInfo *TRI) const { 1063 MachineFunction &MF = *MBB.getParent(); 1064 SmallVector<MachineInstr*, 4> NewMIs; 1065 1066 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1067 FuncInfo->setHasSpills(); 1068 1069 bool NonRI = false, SpillsVRS = false; 1070 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs, 1071 NonRI, SpillsVRS)) 1072 FuncInfo->setSpillsCR(); 1073 1074 if (SpillsVRS) 1075 FuncInfo->setSpillsVRSAVE(); 1076 1077 if (NonRI) 1078 FuncInfo->setHasNonRISpills(); 1079 1080 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 1081 MBB.insert(MI, NewMIs[i]); 1082 1083 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 1084 MachineMemOperand *MMO = MF.getMachineMemOperand( 1085 MachinePointerInfo::getFixedStack(MF, FrameIdx), 1086 MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx), 1087 MFI.getObjectAlignment(FrameIdx)); 1088 NewMIs.back()->addMemOperand(MF, MMO); 1089} 1090 1091bool PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, 1092 unsigned DestReg, int FrameIdx, 1093 const TargetRegisterClass *RC, 1094 SmallVectorImpl<MachineInstr *> &NewMIs, 1095 bool &NonRI, bool &SpillsVRS) const { 1096 // Note: If additional load instructions are added here, 1097 // update isLoadFromStackSlot. 1098 1099 if (PPC::GPRCRegClass.hasSubClassEq(RC) || 1100 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { 1101 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 1102 DestReg), FrameIdx)); 1103 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) || 1104 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) { 1105 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg), 1106 FrameIdx)); 1107 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { 1108 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg), 1109 FrameIdx)); 1110 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { 1111 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg), 1112 FrameIdx)); 1113 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { 1114 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, 1115 get(PPC::RESTORE_CR), DestReg), 1116 FrameIdx)); 1117 return true; 1118 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { 1119 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, 1120 get(PPC::RESTORE_CRBIT), DestReg), 1121 FrameIdx)); 1122 return true; 1123 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { 1124 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg), 1125 FrameIdx)); 1126 NonRI = true; 1127 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) { 1128 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXVD2X), DestReg), 1129 FrameIdx)); 1130 NonRI = true; 1131 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) { 1132 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSDX), DestReg), 1133 FrameIdx)); 1134 NonRI = true; 1135 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) { 1136 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSSPX), DestReg), 1137 FrameIdx)); 1138 NonRI = true; 1139 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) { 1140 assert(Subtarget.isDarwin() && 1141 "VRSAVE only needs spill/restore on Darwin"); 1142 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, 1143 get(PPC::RESTORE_VRSAVE), 1144 DestReg), 1145 FrameIdx)); 1146 SpillsVRS = true; 1147 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) { 1148 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDX), DestReg), 1149 FrameIdx)); 1150 NonRI = true; 1151 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) { 1152 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFSXs), DestReg), 1153 FrameIdx)); 1154 NonRI = true; 1155 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) { 1156 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDXb), DestReg), 1157 FrameIdx)); 1158 NonRI = true; 1159 } else { 1160 llvm_unreachable("Unknown regclass!"); 1161 } 1162 1163 return false; 1164} 1165 1166void 1167PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 1168 MachineBasicBlock::iterator MI, 1169 unsigned DestReg, int FrameIdx, 1170 const TargetRegisterClass *RC, 1171 const TargetRegisterInfo *TRI) const { 1172 MachineFunction &MF = *MBB.getParent(); 1173 SmallVector<MachineInstr*, 4> NewMIs; 1174 DebugLoc DL; 1175 if (MI != MBB.end()) DL = MI->getDebugLoc(); 1176 1177 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1178 FuncInfo->setHasSpills(); 1179 1180 bool NonRI = false, SpillsVRS = false; 1181 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs, 1182 NonRI, SpillsVRS)) 1183 FuncInfo->setSpillsCR(); 1184 1185 if (SpillsVRS) 1186 FuncInfo->setSpillsVRSAVE(); 1187 1188 if (NonRI) 1189 FuncInfo->setHasNonRISpills(); 1190 1191 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 1192 MBB.insert(MI, NewMIs[i]); 1193 1194 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 1195 MachineMemOperand *MMO = MF.getMachineMemOperand( 1196 MachinePointerInfo::getFixedStack(MF, FrameIdx), 1197 MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx), 1198 MFI.getObjectAlignment(FrameIdx)); 1199 NewMIs.back()->addMemOperand(MF, MMO); 1200} 1201 1202bool PPCInstrInfo:: 1203ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 1204 assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); 1205 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR) 1206 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0); 1207 else 1208 // Leave the CR# the same, but invert the condition. 1209 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); 1210 return false; 1211} 1212 1213bool PPCInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, 1214 unsigned Reg, MachineRegisterInfo *MRI) const { 1215 // For some instructions, it is legal to fold ZERO into the RA register field. 1216 // A zero immediate should always be loaded with a single li. 1217 unsigned DefOpc = DefMI.getOpcode(); 1218 if (DefOpc != PPC::LI && DefOpc != PPC::LI8) 1219 return false; 1220 if (!DefMI.getOperand(1).isImm()) 1221 return false; 1222 if (DefMI.getOperand(1).getImm() != 0) 1223 return false; 1224 1225 // Note that we cannot here invert the arguments of an isel in order to fold 1226 // a ZERO into what is presented as the second argument. All we have here 1227 // is the condition bit, and that might come from a CR-logical bit operation. 1228 1229 const MCInstrDesc &UseMCID = UseMI.getDesc(); 1230 1231 // Only fold into real machine instructions. 1232 if (UseMCID.isPseudo()) 1233 return false; 1234 1235 unsigned UseIdx; 1236 for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx) 1237 if (UseMI.getOperand(UseIdx).isReg() && 1238 UseMI.getOperand(UseIdx).getReg() == Reg) 1239 break; 1240 1241 assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI"); 1242 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg"); 1243 1244 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx]; 1245 1246 // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0 1247 // register (which might also be specified as a pointer class kind). 1248 if (UseInfo->isLookupPtrRegClass()) { 1249 if (UseInfo->RegClass /* Kind */ != 1) 1250 return false; 1251 } else { 1252 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID && 1253 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID) 1254 return false; 1255 } 1256 1257 // Make sure this is not tied to an output register (or otherwise 1258 // constrained). This is true for ST?UX registers, for example, which 1259 // are tied to their output registers. 1260 if (UseInfo->Constraints != 0) 1261 return false; 1262 1263 unsigned ZeroReg; 1264 if (UseInfo->isLookupPtrRegClass()) { 1265 bool isPPC64 = Subtarget.isPPC64(); 1266 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; 1267 } else { 1268 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? 1269 PPC::ZERO8 : PPC::ZERO; 1270 } 1271 1272 bool DeleteDef = MRI->hasOneNonDBGUse(Reg); 1273 UseMI.getOperand(UseIdx).setReg(ZeroReg); 1274 1275 if (DeleteDef) 1276 DefMI.eraseFromParent(); 1277 1278 return true; 1279} 1280 1281static bool MBBDefinesCTR(MachineBasicBlock &MBB) { 1282 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end(); 1283 I != IE; ++I) 1284 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8)) 1285 return true; 1286 return false; 1287} 1288 1289// We should make sure that, if we're going to predicate both sides of a 1290// condition (a diamond), that both sides don't define the counter register. We 1291// can predicate counter-decrement-based branches, but while that predicates 1292// the branching, it does not predicate the counter decrement. If we tried to 1293// merge the triangle into one predicated block, we'd decrement the counter 1294// twice. 1295bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB, 1296 unsigned NumT, unsigned ExtraT, 1297 MachineBasicBlock &FMBB, 1298 unsigned NumF, unsigned ExtraF, 1299 BranchProbability Probability) const { 1300 return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB)); 1301} 1302 1303 1304bool PPCInstrInfo::isPredicated(const MachineInstr &MI) const { 1305 // The predicated branches are identified by their type, not really by the 1306 // explicit presence of a predicate. Furthermore, some of them can be 1307 // predicated more than once. Because if conversion won't try to predicate 1308 // any instruction which already claims to be predicated (by returning true 1309 // here), always return false. In doing so, we let isPredicable() be the 1310 // final word on whether not the instruction can be (further) predicated. 1311 1312 return false; 1313} 1314 1315bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const { 1316 if (!MI.isTerminator()) 1317 return false; 1318 1319 // Conditional branch is a special case. 1320 if (MI.isBranch() && !MI.isBarrier()) 1321 return true; 1322 1323 return !isPredicated(MI); 1324} 1325 1326bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI, 1327 ArrayRef<MachineOperand> Pred) const { 1328 unsigned OpC = MI.getOpcode(); 1329 if (OpC == PPC::BLR || OpC == PPC::BLR8) { 1330 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { 1331 bool isPPC64 = Subtarget.isPPC64(); 1332 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) 1333 : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR))); 1334 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) { 1335 MI.setDesc(get(PPC::BCLR)); 1336 MachineInstrBuilder(*MI.getParent()->getParent(), MI) 1337 .addReg(Pred[1].getReg()); 1338 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { 1339 MI.setDesc(get(PPC::BCLRn)); 1340 MachineInstrBuilder(*MI.getParent()->getParent(), MI) 1341 .addReg(Pred[1].getReg()); 1342 } else { 1343 MI.setDesc(get(PPC::BCCLR)); 1344 MachineInstrBuilder(*MI.getParent()->getParent(), MI) 1345 .addImm(Pred[0].getImm()) 1346 .addReg(Pred[1].getReg()); 1347 } 1348 1349 return true; 1350 } else if (OpC == PPC::B) { 1351 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { 1352 bool isPPC64 = Subtarget.isPPC64(); 1353 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) 1354 : (isPPC64 ? PPC::BDZ8 : PPC::BDZ))); 1355 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) { 1356 MachineBasicBlock *MBB = MI.getOperand(0).getMBB(); 1357 MI.RemoveOperand(0); 1358 1359 MI.setDesc(get(PPC::BC)); 1360 MachineInstrBuilder(*MI.getParent()->getParent(), MI) 1361 .addReg(Pred[1].getReg()) 1362 .addMBB(MBB); 1363 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { 1364 MachineBasicBlock *MBB = MI.getOperand(0).getMBB(); 1365 MI.RemoveOperand(0); 1366 1367 MI.setDesc(get(PPC::BCn)); 1368 MachineInstrBuilder(*MI.getParent()->getParent(), MI) 1369 .addReg(Pred[1].getReg()) 1370 .addMBB(MBB); 1371 } else { 1372 MachineBasicBlock *MBB = MI.getOperand(0).getMBB(); 1373 MI.RemoveOperand(0); 1374 1375 MI.setDesc(get(PPC::BCC)); 1376 MachineInstrBuilder(*MI.getParent()->getParent(), MI) 1377 .addImm(Pred[0].getImm()) 1378 .addReg(Pred[1].getReg()) 1379 .addMBB(MBB); 1380 } 1381 1382 return true; 1383 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || 1384 OpC == PPC::BCTRL || OpC == PPC::BCTRL8) { 1385 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) 1386 llvm_unreachable("Cannot predicate bctr[l] on the ctr register"); 1387 1388 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8; 1389 bool isPPC64 = Subtarget.isPPC64(); 1390 1391 if (Pred[0].getImm() == PPC::PRED_BIT_SET) { 1392 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) 1393 : (setLR ? PPC::BCCTRL : PPC::BCCTR))); 1394 MachineInstrBuilder(*MI.getParent()->getParent(), MI) 1395 .addReg(Pred[1].getReg()); 1396 return true; 1397 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { 1398 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) 1399 : (setLR ? PPC::BCCTRLn : PPC::BCCTRn))); 1400 MachineInstrBuilder(*MI.getParent()->getParent(), MI) 1401 .addReg(Pred[1].getReg()); 1402 return true; 1403 } 1404 1405 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) 1406 : (setLR ? PPC::BCCCTRL : PPC::BCCCTR))); 1407 MachineInstrBuilder(*MI.getParent()->getParent(), MI) 1408 .addImm(Pred[0].getImm()) 1409 .addReg(Pred[1].getReg()); 1410 return true; 1411 } 1412 1413 return false; 1414} 1415 1416bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 1417 ArrayRef<MachineOperand> Pred2) const { 1418 assert(Pred1.size() == 2 && "Invalid PPC first predicate"); 1419 assert(Pred2.size() == 2 && "Invalid PPC second predicate"); 1420 1421 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR) 1422 return false; 1423 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR) 1424 return false; 1425 1426 // P1 can only subsume P2 if they test the same condition register. 1427 if (Pred1[1].getReg() != Pred2[1].getReg()) 1428 return false; 1429 1430 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm(); 1431 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm(); 1432 1433 if (P1 == P2) 1434 return true; 1435 1436 // Does P1 subsume P2, e.g. GE subsumes GT. 1437 if (P1 == PPC::PRED_LE && 1438 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ)) 1439 return true; 1440 if (P1 == PPC::PRED_GE && 1441 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ)) 1442 return true; 1443 1444 return false; 1445} 1446 1447bool PPCInstrInfo::DefinesPredicate(MachineInstr &MI, 1448 std::vector<MachineOperand> &Pred) const { 1449 // Note: At the present time, the contents of Pred from this function is 1450 // unused by IfConversion. This implementation follows ARM by pushing the 1451 // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of 1452 // predicate, instructions defining CTR or CTR8 are also included as 1453 // predicate-defining instructions. 1454 1455 const TargetRegisterClass *RCs[] = 1456 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass, 1457 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass }; 1458 1459 bool Found = false; 1460 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1461 const MachineOperand &MO = MI.getOperand(i); 1462 for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) { 1463 const TargetRegisterClass *RC = RCs[c]; 1464 if (MO.isReg()) { 1465 if (MO.isDef() && RC->contains(MO.getReg())) { 1466 Pred.push_back(MO); 1467 Found = true; 1468 } 1469 } else if (MO.isRegMask()) { 1470 for (TargetRegisterClass::iterator I = RC->begin(), 1471 IE = RC->end(); I != IE; ++I) 1472 if (MO.clobbersPhysReg(*I)) { 1473 Pred.push_back(MO); 1474 Found = true; 1475 } 1476 } 1477 } 1478 } 1479 1480 return Found; 1481} 1482 1483bool PPCInstrInfo::isPredicable(MachineInstr &MI) const { 1484 unsigned OpC = MI.getOpcode(); 1485 switch (OpC) { 1486 default: 1487 return false; 1488 case PPC::B: 1489 case PPC::BLR: 1490 case PPC::BLR8: 1491 case PPC::BCTR: 1492 case PPC::BCTR8: 1493 case PPC::BCTRL: 1494 case PPC::BCTRL8: 1495 return true; 1496 } 1497} 1498 1499bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, 1500 unsigned &SrcReg2, int &Mask, 1501 int &Value) const { 1502 unsigned Opc = MI.getOpcode(); 1503 1504 switch (Opc) { 1505 default: return false; 1506 case PPC::CMPWI: 1507 case PPC::CMPLWI: 1508 case PPC::CMPDI: 1509 case PPC::CMPLDI: 1510 SrcReg = MI.getOperand(1).getReg(); 1511 SrcReg2 = 0; 1512 Value = MI.getOperand(2).getImm(); 1513 Mask = 0xFFFF; 1514 return true; 1515 case PPC::CMPW: 1516 case PPC::CMPLW: 1517 case PPC::CMPD: 1518 case PPC::CMPLD: 1519 case PPC::FCMPUS: 1520 case PPC::FCMPUD: 1521 SrcReg = MI.getOperand(1).getReg(); 1522 SrcReg2 = MI.getOperand(2).getReg(); 1523 return true; 1524 } 1525} 1526 1527bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, 1528 unsigned SrcReg2, int Mask, int Value, 1529 const MachineRegisterInfo *MRI) const { 1530 if (DisableCmpOpt) 1531 return false; 1532 1533 int OpC = CmpInstr.getOpcode(); 1534 unsigned CRReg = CmpInstr.getOperand(0).getReg(); 1535 1536 // FP record forms set CR1 based on the execption status bits, not a 1537 // comparison with zero. 1538 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD) 1539 return false; 1540 1541 // The record forms set the condition register based on a signed comparison 1542 // with zero (so says the ISA manual). This is not as straightforward as it 1543 // seems, however, because this is always a 64-bit comparison on PPC64, even 1544 // for instructions that are 32-bit in nature (like slw for example). 1545 // So, on PPC32, for unsigned comparisons, we can use the record forms only 1546 // for equality checks (as those don't depend on the sign). On PPC64, 1547 // we are restricted to equality for unsigned 64-bit comparisons and for 1548 // signed 32-bit comparisons the applicability is more restricted. 1549 bool isPPC64 = Subtarget.isPPC64(); 1550 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW; 1551 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW; 1552 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD; 1553 1554 // Get the unique definition of SrcReg. 1555 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 1556 if (!MI) return false; 1557 int MIOpC = MI->getOpcode(); 1558 1559 bool equalityOnly = false; 1560 bool noSub = false; 1561 if (isPPC64) { 1562 if (is32BitSignedCompare) { 1563 // We can perform this optimization only if MI is sign-extending. 1564 if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo || 1565 MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo || 1566 MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo || 1567 MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo || 1568 MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) { 1569 noSub = true; 1570 } else 1571 return false; 1572 } else if (is32BitUnsignedCompare) { 1573 // 32-bit rotate and mask instructions are zero extending only if MB <= ME 1574 bool isZeroExtendingRotate = 1575 (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINMo || 1576 MIOpC == PPC::RLWNM || MIOpC == PPC::RLWNMo) 1577 && MI->getOperand(3).getImm() <= MI->getOperand(4).getImm(); 1578 1579 // We can perform this optimization, equality only, if MI is 1580 // zero-extending. 1581 if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo || 1582 MIOpC == PPC::SLW || MIOpC == PPC::SLWo || 1583 MIOpC == PPC::SRW || MIOpC == PPC::SRWo || 1584 isZeroExtendingRotate) { 1585 noSub = true; 1586 equalityOnly = true; 1587 } else 1588 return false; 1589 } else 1590 equalityOnly = is64BitUnsignedCompare; 1591 } else 1592 equalityOnly = is32BitUnsignedCompare; 1593 1594 if (equalityOnly) { 1595 // We need to check the uses of the condition register in order to reject 1596 // non-equality comparisons. 1597 for (MachineRegisterInfo::use_instr_iterator I =MRI->use_instr_begin(CRReg), 1598 IE = MRI->use_instr_end(); I != IE; ++I) { 1599 MachineInstr *UseMI = &*I; 1600 if (UseMI->getOpcode() == PPC::BCC) { 1601 unsigned Pred = UseMI->getOperand(0).getImm(); 1602 if (Pred != PPC::PRED_EQ && Pred != PPC::PRED_NE) 1603 return false; 1604 } else if (UseMI->getOpcode() == PPC::ISEL || 1605 UseMI->getOpcode() == PPC::ISEL8) { 1606 unsigned SubIdx = UseMI->getOperand(3).getSubReg(); 1607 if (SubIdx != PPC::sub_eq) 1608 return false; 1609 } else 1610 return false; 1611 } 1612 } 1613 1614 MachineBasicBlock::iterator I = CmpInstr; 1615 1616 // Scan forward to find the first use of the compare. 1617 for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL; 1618 ++I) { 1619 bool FoundUse = false; 1620 for (MachineRegisterInfo::use_instr_iterator J =MRI->use_instr_begin(CRReg), 1621 JE = MRI->use_instr_end(); J != JE; ++J) 1622 if (&*J == &*I) { 1623 FoundUse = true; 1624 break; 1625 } 1626 1627 if (FoundUse) 1628 break; 1629 } 1630 1631 // There are two possible candidates which can be changed to set CR[01]. 1632 // One is MI, the other is a SUB instruction. 1633 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1). 1634 MachineInstr *Sub = nullptr; 1635 if (SrcReg2 != 0) 1636 // MI is not a candidate for CMPrr. 1637 MI = nullptr; 1638 // FIXME: Conservatively refuse to convert an instruction which isn't in the 1639 // same BB as the comparison. This is to allow the check below to avoid calls 1640 // (and other explicit clobbers); instead we should really check for these 1641 // more explicitly (in at least a few predecessors). 1642 else if (MI->getParent() != CmpInstr.getParent() || Value != 0) { 1643 // PPC does not have a record-form SUBri. 1644 return false; 1645 } 1646 1647 // Search for Sub. 1648 const TargetRegisterInfo *TRI = &getRegisterInfo(); 1649 --I; 1650 1651 // Get ready to iterate backward from CmpInstr. 1652 MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin(); 1653 1654 for (; I != E && !noSub; --I) { 1655 const MachineInstr &Instr = *I; 1656 unsigned IOpC = Instr.getOpcode(); 1657 1658 if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) || 1659 Instr.readsRegister(PPC::CR0, TRI))) 1660 // This instruction modifies or uses the record condition register after 1661 // the one we want to change. While we could do this transformation, it 1662 // would likely not be profitable. This transformation removes one 1663 // instruction, and so even forcing RA to generate one move probably 1664 // makes it unprofitable. 1665 return false; 1666 1667 // Check whether CmpInstr can be made redundant by the current instruction. 1668 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW || 1669 OpC == PPC::CMPD || OpC == PPC::CMPLD) && 1670 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) && 1671 ((Instr.getOperand(1).getReg() == SrcReg && 1672 Instr.getOperand(2).getReg() == SrcReg2) || 1673 (Instr.getOperand(1).getReg() == SrcReg2 && 1674 Instr.getOperand(2).getReg() == SrcReg))) { 1675 Sub = &*I; 1676 break; 1677 } 1678 1679 if (I == B) 1680 // The 'and' is below the comparison instruction. 1681 return false; 1682 } 1683 1684 // Return false if no candidates exist. 1685 if (!MI && !Sub) 1686 return false; 1687 1688 // The single candidate is called MI. 1689 if (!MI) MI = Sub; 1690 1691 int NewOpC = -1; 1692 MIOpC = MI->getOpcode(); 1693 if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8) 1694 NewOpC = MIOpC; 1695 else { 1696 NewOpC = PPC::getRecordFormOpcode(MIOpC); 1697 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1) 1698 NewOpC = MIOpC; 1699 } 1700 1701 // FIXME: On the non-embedded POWER architectures, only some of the record 1702 // forms are fast, and we should use only the fast ones. 1703 1704 // The defining instruction has a record form (or is already a record 1705 // form). It is possible, however, that we'll need to reverse the condition 1706 // code of the users. 1707 if (NewOpC == -1) 1708 return false; 1709 1710 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate; 1711 SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate; 1712 1713 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP 1714 // needs to be updated to be based on SUB. Push the condition code 1715 // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the 1716 // condition code of these operands will be modified. 1717 bool ShouldSwap = false; 1718 if (Sub) { 1719 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 1720 Sub->getOperand(2).getReg() == SrcReg; 1721 1722 // The operands to subf are the opposite of sub, so only in the fixed-point 1723 // case, invert the order. 1724 ShouldSwap = !ShouldSwap; 1725 } 1726 1727 if (ShouldSwap) 1728 for (MachineRegisterInfo::use_instr_iterator 1729 I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end(); 1730 I != IE; ++I) { 1731 MachineInstr *UseMI = &*I; 1732 if (UseMI->getOpcode() == PPC::BCC) { 1733 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm(); 1734 assert((!equalityOnly || 1735 Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) && 1736 "Invalid predicate for equality-only optimization"); 1737 PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)), 1738 PPC::getSwappedPredicate(Pred))); 1739 } else if (UseMI->getOpcode() == PPC::ISEL || 1740 UseMI->getOpcode() == PPC::ISEL8) { 1741 unsigned NewSubReg = UseMI->getOperand(3).getSubReg(); 1742 assert((!equalityOnly || NewSubReg == PPC::sub_eq) && 1743 "Invalid CR bit for equality-only optimization"); 1744 1745 if (NewSubReg == PPC::sub_lt) 1746 NewSubReg = PPC::sub_gt; 1747 else if (NewSubReg == PPC::sub_gt) 1748 NewSubReg = PPC::sub_lt; 1749 1750 SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)), 1751 NewSubReg)); 1752 } else // We need to abort on a user we don't understand. 1753 return false; 1754 } 1755 1756 // Create a new virtual register to hold the value of the CR set by the 1757 // record-form instruction. If the instruction was not previously in 1758 // record form, then set the kill flag on the CR. 1759 CmpInstr.eraseFromParent(); 1760 1761 MachineBasicBlock::iterator MII = MI; 1762 BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(), 1763 get(TargetOpcode::COPY), CRReg) 1764 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0); 1765 1766 // Even if CR0 register were dead before, it is alive now since the 1767 // instruction we just built uses it. 1768 MI->clearRegisterDeads(PPC::CR0); 1769 1770 if (MIOpC != NewOpC) { 1771 // We need to be careful here: we're replacing one instruction with 1772 // another, and we need to make sure that we get all of the right 1773 // implicit uses and defs. On the other hand, the caller may be holding 1774 // an iterator to this instruction, and so we can't delete it (this is 1775 // specifically the case if this is the instruction directly after the 1776 // compare). 1777 1778 const MCInstrDesc &NewDesc = get(NewOpC); 1779 MI->setDesc(NewDesc); 1780 1781 if (NewDesc.ImplicitDefs) 1782 for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs(); 1783 *ImpDefs; ++ImpDefs) 1784 if (!MI->definesRegister(*ImpDefs)) 1785 MI->addOperand(*MI->getParent()->getParent(), 1786 MachineOperand::CreateReg(*ImpDefs, true, true)); 1787 if (NewDesc.ImplicitUses) 1788 for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses(); 1789 *ImpUses; ++ImpUses) 1790 if (!MI->readsRegister(*ImpUses)) 1791 MI->addOperand(*MI->getParent()->getParent(), 1792 MachineOperand::CreateReg(*ImpUses, false, true)); 1793 } 1794 assert(MI->definesRegister(PPC::CR0) && 1795 "Record-form instruction does not define cr0?"); 1796 1797 // Modify the condition code of operands in OperandsToUpdate. 1798 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to 1799 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 1800 for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++) 1801 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second); 1802 1803 for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++) 1804 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second); 1805 1806 return true; 1807} 1808 1809/// GetInstSize - Return the number of bytes of code the specified 1810/// instruction may be. This returns the maximum number of bytes. 1811/// 1812unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const { 1813 unsigned Opcode = MI.getOpcode(); 1814 1815 if (Opcode == PPC::INLINEASM) { 1816 const MachineFunction *MF = MI.getParent()->getParent(); 1817 const char *AsmStr = MI.getOperand(0).getSymbolName(); 1818 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); 1819 } else if (Opcode == TargetOpcode::STACKMAP) { 1820 return MI.getOperand(1).getImm(); 1821 } else if (Opcode == TargetOpcode::PATCHPOINT) { 1822 PatchPointOpers Opers(&MI); 1823 return Opers.getMetaOper(PatchPointOpers::NBytesPos).getImm(); 1824 } else { 1825 const MCInstrDesc &Desc = get(Opcode); 1826 return Desc.getSize(); 1827 } 1828} 1829 1830std::pair<unsigned, unsigned> 1831PPCInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const { 1832 const unsigned Mask = PPCII::MO_ACCESS_MASK; 1833 return std::make_pair(TF & Mask, TF & ~Mask); 1834} 1835 1836ArrayRef<std::pair<unsigned, const char *>> 1837PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags() const { 1838 using namespace PPCII; 1839 static const std::pair<unsigned, const char *> TargetFlags[] = { 1840 {MO_LO, "ppc-lo"}, 1841 {MO_HA, "ppc-ha"}, 1842 {MO_TPREL_LO, "ppc-tprel-lo"}, 1843 {MO_TPREL_HA, "ppc-tprel-ha"}, 1844 {MO_DTPREL_LO, "ppc-dtprel-lo"}, 1845 {MO_TLSLD_LO, "ppc-tlsld-lo"}, 1846 {MO_TOC_LO, "ppc-toc-lo"}, 1847 {MO_TLS, "ppc-tls"}}; 1848 return makeArrayRef(TargetFlags); 1849} 1850 1851ArrayRef<std::pair<unsigned, const char *>> 1852PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const { 1853 using namespace PPCII; 1854 static const std::pair<unsigned, const char *> TargetFlags[] = { 1855 {MO_PLT, "ppc-plt"}, 1856 {MO_PIC_FLAG, "ppc-pic"}, 1857 {MO_NLP_FLAG, "ppc-nlp"}, 1858 {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}}; 1859 return makeArrayRef(TargetFlags); 1860} 1861 1862bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { 1863 switch (MI.getOpcode()) { 1864 case TargetOpcode::LOAD_STACK_GUARD: { 1865 assert(Subtarget.isTargetLinux() && 1866 "Only Linux target is expected to contain LOAD_STACK_GUARD"); 1867 const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008; 1868 const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2; 1869 MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ)); 1870 MachineInstrBuilder(*MI.getParent()->getParent(), MI) 1871 .addImm(Offset) 1872 .addReg(Reg); 1873 return true; 1874 } 1875 } 1876 return false; 1877} 1878