Searched refs:dsll (Results 1 - 25 of 30) sorted by relevance

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/external/llvm/test/MC/Mips/
H A Dmacro-dla.s12 # CHECK: dsll $5, $5, 16 # encoding: [0x00,0x05,0x2c,0x38]
15 # CHECK: dsll $5, $5, 16 # encoding: [0x00,0x05,0x2c,0x38]
18 # CHECK: dsll $5, $5, 16 # encoding: [0x00,0x05,0x2c,0x38]
26 # CHECK: dsll $5, $5, 16 # encoding: [0x00,0x05,0x2c,0x38]
28 # CHECK: dsll $5, $5, 16 # encoding: [0x00,0x05,0x2c,0x38]
30 # CHECK: dsll $5, $5, 16 # encoding: [0x00,0x05,0x2c,0x38]
32 # CHECK: dsll $5, $5, 16 # encoding: [0x00,0x05,0x2c,0x38]
40 # CHECK: dsll $5, $5, 16 # encoding: [0x00,0x05,0x2c,0x38]
49 # CHECK: dsll $5, $5, 16 # encoding: [0x00,0x05,0x2c,0x38]
58 # CHECK: dsll
[all...]
H A Dmacro-dli.s12 # CHECK: dsll $5, $5, 16 # encoding: [0x00,0x05,0x2c,0x38]
15 # CHECK: dsll $5, $5, 16 # encoding: [0x00,0x05,0x2c,0x38]
18 # CHECK: dsll $5, $5, 16 # encoding: [0x00,0x05,0x2c,0x38]
26 # CHECK: dsll $5, $5, 16 # encoding: [0x00,0x05,0x2c,0x38]
28 # CHECK: dsll $5, $5, 16 # encoding: [0x00,0x05,0x2c,0x38]
30 # CHECK: dsll $5, $5, 16 # encoding: [0x00,0x05,0x2c,0x38]
32 # CHECK: dsll $5, $5, 16 # encoding: [0x00,0x05,0x2c,0x38]
40 # CHECK: dsll $5, $5, 16 # encoding: [0x00,0x05,0x2c,0x38]
49 # CHECK: dsll $5, $5, 16 # encoding: [0x00,0x05,0x2c,0x38]
58 # CHECK: dsll
[all...]
H A Dmips64-expansions.s7 # CHECK-NOT: dsll
12 # CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
14 # CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
22 # CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
24 # CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
31 # CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
33 # CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
41 # CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
43 # CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
51 # CHECK: dsll
[all...]
H A Delf-gprel-32-64.s41 dsll $3, $4, 32
H A Ddo_switch3.s32 dsll $3, $1, 32
H A Drotations64.s105 # CHECK-64: dsll $1, $4, 1 # encoding: [0x00,0x04,0x08,0x78]
113 # CHECK-64: dsll $1, $5, 1 # encoding: [0x00,0x05,0x08,0x78]
118 # CHECK-64: dsll $1, $5, 31 # encoding: [0x00,0x05,0x0f,0xf8]
141 # CHECK-64: dsll $1, $5, 1 # encoding: [0x00,0x05,0x08,0x78]
146 # CHECK-64: dsll $1, $5, 31 # encoding: [0x00,0x05,0x0f,0xf8]
203 # CHECK-64: dsll $4, $5, 31 # encoding: [0x00,0x05,0x27,0xf8]
208 # CHECK-64: dsll $4, $5, 1 # encoding: [0x00,0x05,0x20,0x78]
231 # CHECK-64: dsll $4, $5, 31 # encoding: [0x00,0x05,0x27,0xf8]
236 # CHECK-64: dsll $4, $5, 1 # encoding: [0x00,0x05,0x20,0x78]
/external/llvm/test/MC/Mips/mips1/
H A Dinvalid-mips3.s32 dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
33 dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
34 dsll $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips4.s28 dsll $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
29 dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
30 dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips5.s27 dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
28 dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
29 dsll $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips2/
H A Dinvalid-mips3.s28 dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
29 dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
30 dsll $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips4.s26 dsll $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
27 dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
28 dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips5.s25 dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
26 dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
27 dsll $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips3/
H A Dvalid.s83 dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8]
84 dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8]
85 dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
/external/llvm/test/MC/Mips/mips4/
H A Dvalid.s87 dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8]
88 dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8]
89 dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
/external/llvm/test/MC/Mips/mips5/
H A Dvalid.s87 dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8]
88 dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8]
89 dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
/external/llvm/test/MC/Mips/mips64/
H A Dvalid.s94 dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8]
95 dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8]
96 dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
/external/llvm/test/MC/Mips/mips64r2/
H A Dvalid.s103 dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8]
104 dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8]
105 dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
/external/llvm/test/MC/Mips/mips64r3/
H A Dvalid.s103 dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8]
104 dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8]
105 dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
/external/llvm/test/MC/Mips/mips64r5/
H A Dvalid.s103 dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8]
104 dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8]
105 dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
/external/v8/src/builtins/mips64/
H A Dbuiltins-mips64.cc895 __ dsll(a7, argc, kPointerSizeLog2);
1156 __ dsll(scratch2, num_args, kPointerSizeLog2);
1170 __ dsll(scratch2, scratch2, kPointerSizeLog2);
2270 __ dsll(at, len, kPointerSizeLog2);
2293 __ dsll(scratch, len, kPointerSizeLog2);
2631 __ dsll(a5, a4, kPointerSizeLog2);
2853 __ dsll(at, spread_len, kPointerSizeLog2);
2936 __ dsll(a5, a4, kPointerSizeLog2);
3151 __ dsll(a4, a2, kPointerSizeLog2);
3207 __ dsll(a
[all...]
/external/v8/src/crankshaft/mips64/
H A Dlithium-codegen-mips64.cc1391 __ dsll(result, left, shift);
1401 __ dsll(scratch, left, shift);
1649 __ dsll(result, left, shift_count);
1755 __ dsll(scratch, ToRegister(index), 1);
2804 __ dsll(scratch0(), key, shift_size);
2889 __ dsll(at, key, shift_size);
3008 __ dsll(scratch0(), key, shift_size);
3023 __ dsll(scratch0(), key, shift_size);
3176 __ dsll(scratch, length, kPointerSizeLog2);
3183 __ dsll(scratc
[all...]
/external/llvm/test/MC/Mips/micromips64r6/
H A Dinvalid.s247 dsll $3, $4, 64 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
248 dsll $3, $4, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
H A Dvalid.s274 dsll $3, $4, 5 # CHECK: dsll $3, $4, 5 # encoding: [0x58,0x64,0x28,0x00]
/external/v8/src/mips64/
H A Dmacro-assembler-mips64.cc1173 dsll(tmp, rs, sa);
1327 dsll(rd, rd, 8);
1357 dsll(rd, rd, 8);
1571 dsll(rd, rd, 16);
1581 dsll(rd, rd, 16);
1584 dsll(rd, rd, 16);
1587 dsll(rd, rd, 16);
1604 dsll(rd, rd, 16);
1611 dsll(rd, rd, 16);
1635 dsll(r
[all...]
/external/v8/src/regexp/mips64/
H A Dregexp-macro-assembler-mips64.cc722 __ dsll(t1, a1, (mode_ == UC16) ? 1 : 0);

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