| /external/llvm/test/MC/Mips/ |
| H A D | macro-ddiv.s | 13 # CHECK-NOTRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
26 # CHECK-NOTRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
42 # CHECK-NOTRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
58 # CHECK-NOTRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
79 # CHECK-TRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
89 # CHECK-TRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
102 # CHECK-TRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
115 # CHECK-TRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
|
| H A D | rotations64.s | 123 # CHECK-64: dsll32 $1, $5, 0 # encoding: [0x00,0x05,0x08,0x3c]
128 # CHECK-64: dsll32 $1, $5, 1 # encoding: [0x00,0x05,0x08,0x7c]
133 # CHECK-64: dsll32 $1, $5, 31 # encoding: [0x00,0x05,0x0f,0xfc]
151 # CHECK-64: dsll32 $1, $5, 0 # encoding: [0x00,0x05,0x08,0x3c]
156 # CHECK-64: dsll32 $1, $5, 1 # encoding: [0x00,0x05,0x08,0x7c]
161 # CHECK-64: dsll32 $1, $5, 31 # encoding: [0x00,0x05,0x0f,0xfc]
180 # CHECK-64: dsll32 $4, $4, 31 # encoding: [0x00,0x04,0x27,0xfc]
188 # CHECK-64: dsll32 $4, $5, 31 # encoding: [0x00,0x05,0x27,0xfc]
193 # CHECK-64: dsll32 $4, $5, 1 # encoding: [0x00,0x05,0x20,0x7c]
198 # CHECK-64: dsll32
[all...] |
| H A D | macro-dla.s | 82 # CHECK: dsll32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3c]
85 # CHECK: dsll32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3c]
88 # CHECK: dsll32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3c]
91 # CHECK: dsll32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3c]
187 # CHECK: dsll32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3c]
190 # CHECK: dsll32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3c]
193 # CHECK: dsll32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3c]
196 # CHECK: dsll32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3c]
294 # CHECK: dsll32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3c]
297 # CHECK: dsll32
[all...] |
| H A D | macro-dli.s | 82 # CHECK: dsll32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3c]
85 # CHECK: dsll32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3c]
88 # CHECK: dsll32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3c]
91 # CHECK: dsll32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3c]
187 # CHECK: dsll32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3c]
190 # CHECK: dsll32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3c]
193 # CHECK: dsll32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3c]
196 # CHECK: dsll32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3c]
294 # CHECK: dsll32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3c]
297 # CHECK: dsll32
[all...] |
| /external/llvm/test/MC/Mips/mips1/ |
| H A D | invalid-mips3.s | 35 dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
36 dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips4.s | 31 dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
32 dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips5.s | 30 dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
31 dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips3.s | 31 dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
32 dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips4.s | 29 dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
30 dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips5.s | 28 dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
29 dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips3/ |
| H A D | valid.s | 86 dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
87 dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | valid.s | 90 dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
91 dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
|
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | valid.s | 90 dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
91 dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | valid.s | 97 dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
98 dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 106 dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
107 dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| H A D | valid.s | 106 dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
107 dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| H A D | valid.s | 106 dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
107 dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| H A D | invalid.s | 249 dsll32 $3, $4, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
250 dsll32 $3, $4, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
|
| H A D | valid.s | 275 dsll32 $3, $4, 5 # CHECK: dsll32 $3, $4, 5 # encoding: [0x58,0x64,0x28,0x08]
|
| /external/v8/src/mips64/ |
| H A D | disasm-mips64.cc | 1181 Format(instr, "dsll32 'rd, 'rt, 'sa");
|
| H A D | macro-assembler-mips64.cc | 1240 dsll32(src, src, 0);
1427 dsll32(scratch, scratch, 0);
1591 dsll32(rd, rd, 0);
1594 dsll32(rd, rd, 0);
4026 dsll32(src, src, 0);
4028 dsll32(scratch, scratch, 0);
4039 dsll32(dst, dst, 0);
6203 dsll32(t8, t8, 0);
6247 dsll32(t8, t8, 0);
|
| H A D | macro-assembler-mips64.h | 1577 dsll32(dst, src, 0);
1782 dsll32(dst, dst, 0);
|
| H A D | assembler-mips64.h | 801 void dsll32(Register rt, Register rd, uint16_t sa);
|
| /external/v8/src/builtins/mips64/ |
| H A D | builtins-mips64.cc | 2140 __ dsll32(a0, a0, 0);
|
| /external/v8/src/compiler/mips64/ |
| H A D | code-generator-mips64.cc | 1251 __ dsll32(i.OutputRegister(), i.InputRegister(0),
|