| /external/llvm/test/MC/Mips/ |
| H A D | mips64-alu-instructions.s | 85 # CHECK: dsubu $4, $3, $5 # encoding: [0x2f,0x20,0x65,0x00]
110 dsubu $4,$3,$5
111 dsubu $9,$6,17767
125 # CHECK: dsubu $9, $9, $3 # encoding: [0x2f,0x48,0x23,0x01]
136 dsubu $9, $3
138 dsubu $9, 10
151 dsubu $9, $3, 8 * 4
152 dsubu $9, $3, (8 * 4)
|
| H A D | rotations64.s | 90 # CHECK-64: dsubu $1, $zero, $5 # encoding: [0x00,0x05,0x08,0x2f]
94 # CHECK-64R: dsubu $1, $zero, $5 # encoding: [0x00,0x05,0x08,0x2f]
97 # CHECK-64: dsubu $1, $zero, $6 # encoding: [0x00,0x06,0x08,0x2f]
101 # CHECK-64R: dsubu $4, $zero, $6 # encoding: [0x00,0x06,0x20,0x2f]
167 # CHECK-64: dsubu $1, $zero, $5 # encoding: [0x00,0x05,0x08,0x2f]
173 # CHECK-64: dsubu $1, $zero, $6 # encoding: [0x00,0x06,0x08,0x2f]
|
| /external/libffi/src/mips/ |
| H A D | ffitarget.h | 157 # define SUBU dsubu
|
| /external/python/cpython2/Modules/_ctypes/libffi/src/mips/ |
| H A D | ffitarget.h | 157 # define SUBU dsubu
|
| /external/python/cpython3/Modules/_ctypes/libffi/src/mips/ |
| H A D | ffitarget.h | 157 # define SUBU dsubu
|
| /external/capstone/suite/MC/Mips/ |
| H A D | mips64-alu-instructions.s.cs | 46 0x2f,0x20,0x65,0x00 = dsubu $4, $3, $5
|
| /external/llvm/test/MC/Mips/mips1/ |
| H A D | invalid-mips3.s | 50 dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
51 dsubu $15,$11,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
52 dsubu $14,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips4.s | 47 dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips5.s | 45 dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips3.s | 47 dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
48 dsubu $15,$11,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
49 dsubu $14,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips4.s | 45 dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips5.s | 43 dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 127 dsubu $a1,$a1,$k0
128 dsubu $a1,$a1,$k0
129 dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
130 dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| H A D | valid.s | 127 dsubu $a1,$a1,$k0
128 dsubu $a1,$a1,$k0
129 dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
130 dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| H A D | valid.s | 127 dsubu $a1,$a1,$k0
128 dsubu $a1,$a1,$k0
129 dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
130 dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea]
|
| /external/llvm/test/MC/Mips/mips3/ |
| H A D | valid.s | 106 dsubu $a1,$a1,$k0
107 dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
108 dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea]
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | valid.s | 110 dsubu $a1,$a1,$k0
111 dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
112 dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea]
|
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | valid.s | 110 dsubu $a1,$a1,$k0
111 dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
112 dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea]
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | valid.s | 117 dsubu $a1,$a1,$k0
118 dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
119 dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea]
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| H A D | valid.s | 230 dsubu $3, 5 # CHECK: daddiu $3, $3, -5 # encoding: [0x5c,0x63,0xff,0xfb]
231 dsubu $3, $4, 5 # CHECK: daddiu $3, $4, -5 # encoding: [0x5c,0x64,0xff,0xfb]
257 dsubu $3, $7, $15 # CHECK: dsubu $3, $7, $15 # encoding: [0x59,0xe7,0x19,0xd0]
|
| /external/v8/src/builtins/mips64/ |
| H A D | builtins-mips64.cc | 889 __ dsubu(a2, sp, a2);
1154 __ dsubu(scratch1, sp, scratch1);
3152 __ dsubu(a4, a0, a4);
|
| /external/v8/src/mips64/ |
| H A D | code-stubs-mips64.cc | 538 __ dsubu(v0, a1, a0);
2410 __ dsubu(v0, a0, a1);
2430 __ dsubu(v0, a0, a1);
|
| H A D | assembler-mips64.h | 758 void dsubu(Register rd, Register rs, Register rt);
|
| H A D | macro-assembler-mips64.cc | 615 dsubu(rd, rs, rt.rm());
625 dsubu(rd, rs, at);
5325 dsubu(dst, left, right); // Left is overwritten.
5331 dsubu(dst, left, right); // Right is overwritten.
5336 dsubu(dst, left, right);
|
| /external/valgrind/coregrind/ |
| H A D | m_trampoline.S | 1371 dsubu $v0, $a0, $v0
|