Searched refs:imm (Results 1 - 25 of 383) sorted by relevance

1234567891011>>

/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_fs_combine_constants.cpp101 struct imm { struct
142 struct imm *imm; member in struct:table
147 static struct imm *
151 if (table->imm[i].val == val) {
152 return &table->imm[i];
158 static struct imm *
163 table->imm = reralloc(mem_ctx, table->imm, struct imm, tabl
223 struct imm *imm = find_imm(&table, val); local
253 struct imm *imm = &table.imm[i]; local
273 struct imm *imm = &table.imm[i]; local
309 struct imm *imm = &table.imm[i]; local
[all...]
H A Dbrw_reg.h597 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_DF);
598 imm.df = df;
599 return imm;
605 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F);
606 imm.f = f;
607 return imm;
614 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D);
615 imm.d = d;
616 return imm;
623 struct brw_reg imm
[all...]
/external/llvm/test/MC/AsmParser/
H A Dmacro-irp.s11 .irp imm,4,3,5
12 addl \reg, \imm
/external/llvm/test/MC/X86/
H A Dimm-comments.s20 # CHECK: movw $32767, %ax # imm = 0x7FFF
21 # CHECK: movw $-32768, %ax # imm = 0x8000
23 # CHECK: movl $2147483647, %eax # imm = 0x7FFFFFFF
24 # CHECK: movl $-2147483648, %eax # imm = 0x80000000
26 # CHECK: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
27 # CHECK: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
/external/clang/lib/Headers/
H A Df16cintrin.h59 /// unsigned short _cvtss_sh(float a, const int imm);
67 /// \param imm
75 #define _cvtss_sh(a, imm) \
77 (imm)))[0]))
85 /// __m128i _mm_cvtps_ph(__m128 a, const int imm);
92 /// \param imm
102 #define _mm_cvtps_ph(a, imm) \
103 ((__m128i)__builtin_ia32_vcvtps2ph((__v4sf)(__m128)(a), (imm)))
H A Davx2intrin.h498 #define _mm256_shuffle_epi32(a, imm) __extension__ ({ \
501 0 + (((imm) >> 0) & 0x3), \
502 0 + (((imm) >> 2) & 0x3), \
503 0 + (((imm) >> 4) & 0x3), \
504 0 + (((imm) >> 6) & 0x3), \
505 4 + (((imm) >> 0) & 0x3), \
506 4 + (((imm) >> 2) & 0x3), \
507 4 + (((imm) >> 4) & 0x3), \
508 4 + (((imm) >> 6) & 0x3)); })
510 #define _mm256_shufflehi_epi16(a, imm) __extension_
[all...]
H A Davx512bwintrin.h1632 #define _mm512_shufflehi_epi16(A, imm) __extension__ ({ \
1636 4 + (((imm) >> 0) & 0x3), \
1637 4 + (((imm) >> 2) & 0x3), \
1638 4 + (((imm) >> 4) & 0x3), \
1639 4 + (((imm) >> 6) & 0x3), \
1641 12 + (((imm) >> 0) & 0x3), \
1642 12 + (((imm) >> 2) & 0x3), \
1643 12 + (((imm) >> 4) & 0x3), \
1644 12 + (((imm) >> 6) & 0x3), \
1646 20 + (((imm) >>
[all...]
H A Drtmintrin.h55 #define _xabort(imm) __builtin_ia32_xabort((imm))
/external/vixl/src/aarch32/
H A Dinstructions-aarch32.cc605 ImmediateT32::ImmediateT32(uint32_t imm) { argument
607 if ((imm & ~0xff) == 0) {
608 SetEncodingValue(imm);
611 if ((imm >> 16) == (imm & 0xffff)) {
612 if ((imm & 0xff00) == 0) {
614 SetEncodingValue((imm & 0xff) | (0x1 << 8));
617 if ((imm & 0xff) == 0) {
619 SetEncodingValue(((imm >> 8) & 0xff) | (0x2 << 8));
622 if (((imm >>
645 IsImmediateT32(uint32_t imm) argument
679 ImmediateA32(uint32_t imm) argument
695 IsImmediateA32(uint32_t imm) argument
[all...]
/external/valgrind/none/tests/mips64/
H A Dlogical_instructions.stdout.exp513 andi $t0, $t1, 0xff :: rt 0x0, rs 0x0, imm 0x00ff
514 andi $t2, $t3, 0xffff :: rt 0x0, rs 0x0, imm 0xffff
515 andi $a0, $a1, 0x0 :: rt 0x0, rs 0x0, imm 0x0000
516 andi $s0, $s1, 0x23 :: rt 0x0, rs 0x0, imm 0x0023
517 andi $t0, $t1, 0xff :: rt 0xaa, rs 0x12bd6aa, imm 0x00ff
518 andi $t2, $t3, 0xffff :: rt 0xd6aa, rs 0x12bd6aa, imm 0xffff
519 andi $a0, $a1, 0x0 :: rt 0x0, rs 0x12bd6aa, imm 0x0000
520 andi $s0, $s1, 0x23 :: rt 0x22, rs 0x12bd6aa, imm 0x0023
521 andi $t0, $t1, 0xff :: rt 0x0, rs 0x0, imm 0x00ff
522 andi $t2, $t3, 0xffff :: rt 0x0, rs 0x0, imm
[all...]
H A Dmacro_int.h19 #define TEST2(instruction, RSval, imm, RT, RS) \
31 printf("%s :: rt 0x%llx, rs 0x%llx, imm 0x%04x\n", \
32 instruction, out, (long long) RSval, imm); \
91 #define TEST6(instruction, imm, RT) \
101 printf("%s :: rt 0x%llx, imm 0x%04x\n", \
102 instruction, out, imm); \
/external/pcre/dist2/src/sljit/
H A DsljitNativePPC_32.c29 static sljit_s32 load_immediate(struct sljit_compiler *compiler, sljit_s32 reg, sljit_sw imm) argument
31 if (imm <= SIMM_MAX && imm >= SIMM_MIN)
32 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm));
34 if (!(imm & ~0xffff))
35 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm));
37 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 16)));
38 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS;
101 return push_inst(compiler, ADDI | D(dst) | A(src1) | compiler->imm);
[all...]
H A DsljitNativePPC_64.c44 static sljit_s32 load_immediate(struct sljit_compiler *compiler, sljit_s32 reg, sljit_sw imm) argument
51 if (imm <= SIMM_MAX && imm >= SIMM_MIN)
52 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm));
54 if (!(imm & ~0xffff))
55 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm));
57 if (imm <= 0x7fffffffl && imm >= -0x80000000l) {
58 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 16)));
59 return (imm
[all...]
H A DsljitNativeARM_T2_32.c57 #define IMM3(imm) (imm << 6)
58 #define IMM8(imm) (imm)
76 #define IMM5(imm) \
77 (COPY_BITS(imm, 2, 12, 3) | ((imm & 0x3) << 6))
78 #define IMM12(imm) \
79 (COPY_BITS(imm, 11, 26, 1) | COPY_BITS(imm,
206 emit_imm32_const(struct sljit_compiler *compiler, sljit_s32 dst, sljit_uw imm) argument
428 get_imm(sljit_uw imm) argument
477 load_immediate(struct sljit_compiler *compiler, sljit_s32 dst, sljit_uw imm) argument
517 sljit_uw imm, nimm; local
1568 sljit_uw imm; local
[all...]
/external/capstone/arch/Mips/
H A DMipsInstPrinter.c206 int64_t imm = MCOperand_getImm(Op); local
208 if (imm) { // only print Imm offset if it is not 0
209 if (imm >= 0) {
210 if (imm > HEX_THRESHOLD)
211 SStream_concat(O, "0x%"PRIx64, imm);
213 SStream_concat(O, "%"PRIu64, imm);
215 if (imm < -HEX_THRESHOLD)
216 SStream_concat(O, "-0x%"PRIx64, -imm);
218 SStream_concat(O, "-%"PRIu64, -imm);
222 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm;
249 int64_t imm = MCOperand_getImm(MO); local
274 uint8_t imm = (uint8_t)MCOperand_getImm(MO); local
[all...]
/external/iproute2/include/
H A Dbpf_util.h76 .imm = 0 })
84 .imm = 0 })
94 .imm = IMM })
102 .imm = IMM })
112 .imm = 0 })
120 .imm = 0 })
130 .imm = IMM })
138 .imm = IMM })
150 .imm = (__u32) (IMM) }), \
156 .imm
[all...]
/external/llvm/lib/Target/Sparc/
H A DSparc.h150 inline static unsigned HI22(int64_t imm) { argument
151 return (unsigned)((imm >> 10) & ((1 << 22)-1));
154 inline static unsigned LO10(int64_t imm) { argument
155 return (unsigned)(imm & 0x3FF);
158 inline static unsigned HIX22(int64_t imm) { argument
159 return HI22(~imm);
162 inline static unsigned LOX10(int64_t imm) { argument
163 return ~LO10(~imm);
/external/capstone/arch/X86/
H A DX86ATTInstPrinter.c252 int64_t imm = MCOperand_getImm(Op); local
253 if (imm < 0) {
254 if (imm < -HEX_THRESHOLD)
255 SStream_concat(O, "$-0x%"PRIx64, -imm);
257 SStream_concat(O, "$-%"PRIu64, -imm);
259 if (imm > HEX_THRESHOLD)
260 SStream_concat(O, "$0x%"PRIx64, imm);
262 SStream_concat(O, "$%"PRIu64, imm);
408 int64_t imm = MCOperand_getImm(DispSpec); local
410 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm;
457 int64_t imm = MCOperand_getImm(Op) + MI->flat_insn->size + MI->address; local
514 int64_t imm = MCOperand_getImm(Op); local
[all...]
/external/capstone/bindings/python/capstone/
H A Dmips.py17 ('imm', ctypes.c_int64),
28 def imm(self): member in class:MipsOp
29 return self.value.imm
H A Dsparc.py18 ('imm', ctypes.c_int32),
29 def imm(self): member in class:SparcOp
30 return self.value.imm
H A Dsystemz.py19 ('imm', ctypes.c_int64),
30 def imm(self): member in class:SyszOp
31 return self.value.imm
H A Dxcore.py19 ('imm', ctypes.c_int32),
30 def imm(self): member in class:XcoreOp
31 return self.value.imm
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_bitarit.h66 lp_build_shl_imm(struct lp_build_context *bld, LLVMValueRef a, unsigned imm);
69 lp_build_shr_imm(struct lp_build_context *bld, LLVMValueRef a, unsigned imm);
/external/v8/src/crankshaft/arm64/
H A Ddelayed-masm-arm64-inl.h38 void DelayedMasm::Fmov(FPRegister fd, double imm) { argument
40 __ Fmov(fd, imm);
/external/llvm/test/MC/Mips/
H A Dhex-immediates.s2 # RUN: | llvm-objdump -d --print-imm-hex - | FileCheck %s

Completed in 596 milliseconds

1234567891011>>