Searched refs:lane_size (Results 1 - 4 of 4) sorted by relevance

/external/vixl/src/aarch64/
H A Dassembler-aarch64.cc1804 unsigned lane_size = vt.GetLaneSizeInBytes(); local
1805 VIXL_ASSERT(lane < (kQRegSizeInBytes / lane_size));
1809 lane *= lane_size;
1810 if (lane_size == 8) lane++;
1817 switch (lane_size) {
1828 VIXL_ASSERT(lane_size == 8);
3161 int lane_size = vn.GetLaneSizeInBytes();
3163 switch (lane_size) {
3174 VIXL_ASSERT(lane_size == 8);
3213 int lane_size
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H A Dsimulator-aarch64.cc472 unsigned reg_size, unsigned lane_size) {
473 VIXL_ASSERT(reg_size >= lane_size);
476 if (reg_size != lane_size) {
490 switch (lane_size) {
825 int lane_size = 1 << lane_size_log2; local
836 PrintVRegisterFPHelper(code, lane_size, lane_count);
949 int lane_size = GetPrintRegLaneSizeInBytes(format); local
951 PrintVRegisterRawHelper(reg_code, reg_size, lane_size * lane);
953 PrintVRegisterFPHelper(reg_code, lane_size, lane_count, lane);
4046 int lane_size local
471 GetPrintRegisterFormatForSize( unsigned reg_size, unsigned lane_size) argument
4309 int lane_size = LaneSizeInBytesFromFormat(vf); local
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H A Dlogic-aarch64.cc783 int lane_size = LaneSizeInBitsFromFormat(vform); local
804 dst.SetInt(vform, i, ur >> (64 - lane_size));
1190 int lane_size = LaneSizeInBitsFromFormat(vform); local
1211 dst.SetInt(vform, i, ur >> (64 - lane_size));
H A Dsimulator-aarch64.h1527 unsigned lane_size);

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