Searched refs:lwu (Results 1 - 24 of 24) sorted by relevance

/external/llvm/test/MC/Mips/micromips64r6/
H A Dinvalid-wrong-error.s11 lwu $31, 4096($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
12 lwu $31, 2048($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
13 lwu $31, -2049($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
H A Dvalid.s305 lwu $1, 10($2) # CHECK: lwu $1, 10($2) # encoding: [0x60,0x22,0xe0,0x0a]
/external/llvm/test/MC/Mips/
H A Dmicromips-loadstore-instructions.s25 # CHECK-EL: lwu $2, 8($4) # encoding: [0x44,0x60,0x08,0xe0]
71 # CHECK-EB: lwu $2, 8($4) # encoding: [0x60,0x44,0xe0,0x08]
114 lwu $2, 8($4)
H A Dmicromips-invalid.s91 lwu $32, 4096($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/llvm/test/MC/Mips/mips1/
H A Dinvalid-mips3.s59 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset
H A Dinvalid-mips4.s74 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset
/external/llvm/test/MC/Mips/mips2/
H A Dinvalid-mips3.s55 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:24: error: expected memory with 12-bit signed offset
H A Dinvalid-mips4.s51 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset
/external/llvm/test/MC/Mips/mips3/
H A Dvalid.s139 lwu $s3,-24086($v1)
269 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
/external/llvm/test/MC/Mips/mips4/
H A Dvalid.s144 lwu $s3,-24086($v1)
298 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
/external/llvm/test/MC/Mips/mips5/
H A Dvalid.s145 lwu $s3,-24086($v1)
300 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
/external/llvm/test/MC/Mips/mips64/
H A Dvalid.s152 lwu $s3,-24086($v1)
319 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
/external/llvm/test/MC/Mips/mips64r2/
H A Dvalid.s168 lwu $s3,-24086($v1)
347 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
/external/llvm/test/MC/Mips/mips64r3/
H A Dvalid.s168 lwu $s3,-24086($v1)
346 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
/external/llvm/test/MC/Mips/mips64r5/
H A Dvalid.s169 lwu $s3,-24086($v1)
347 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
/external/v8/src/regexp/mips64/
H A Dregexp-macro-assembler-mips64.cc1031 __ lwu(a0, MemOperand(code_pointer(), cp_offset));
1034 __ lwu(a0, MemOperand(a0, 0));
/external/v8/src/mips64/
H A Ddisasm-mips64.cc1824 Format(instr, "lwu 'rt, 'imm16s('rs)");
H A Dcode-stubs-mips64.cc284 __ lwu(a6, FieldMemOperand(a0, HeapNumber::kExponentOffset));
293 __ lwu(a7, FieldMemOperand(a0, HeapNumber::kMantissaOffset));
2604 __ lwu(hash, FieldMemOperand(key, Name::kHashFieldOffset));
H A Dmacro-assembler-mips64.cc1274 lwu(rd, rs);
1425 lwu(rd, rs);
4993 lwu(exponent, FieldMemOperand(object, HeapNumber::kExponentOffset));
6611 lwu(load_scratch, MemOperand(bitmap_scratch, MemoryChunk::kHeaderSize));
6625 lwu(dst, FieldMemOperand(map, Map::kBitField3Offset));
6632 lwu(dst, FieldMemOperand(map, Map::kBitField3Offset));
H A Dassembler-mips64.h812 void lwu(Register rd, const MemOperand& rs);
H A Dassembler-mips64.cc2050 void Assembler::lwu(Register rd, const MemOperand& rs) { function in class:v8::internal::Assembler
/external/v8/src/crankshaft/mips64/
H A Dlithium-codegen-mips64.cc3320 __ lwu(exponent, FieldMemOperand(input, HeapNumber::kExponentOffset));
3356 __ lwu(exponent, FieldMemOperand(input, HeapNumber::kExponentOffset));
3363 __ lwu(tmp2, FieldMemOperand(input, HeapNumber::kMantissaOffset));
4958 __ lwu(scratch0(), FieldMemOperand(scratch0(), Map::kBitField3Offset));
/external/v8/src/builtins/mips64/
H A Dbuiltins-mips64.cc1768 __ lwu(scratch, FieldMemOperand(map, Map::kBitField3Offset));
/external/v8/src/compiler/mips64/
H A Dcode-generator-mips64.cc1748 __ lwu(i.OutputRegister(), i.MemoryOperand());

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