Searched refs:movz (Results 1 - 25 of 77) sorted by relevance

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/external/llvm/test/MC/AArch64/
H A Dsingle-slash.s6 movz x0, #(32 / 2)
H A Darm64-large-relocs.s4 movz x2, #:abs_g0:sym
6 // CHECK: movz x2, #:abs_g0:sym // encoding: [0bAAA00010,A,0b100AAAAA,0xd2]
14 movz x4, #:abs_g1:sym
16 // CHECK: movz x4, #:abs_g1:sym // encoding: [0bAAA00100,A,0b101AAAAA,0xd2]
24 movz x6, #:abs_g2:sym
26 // CHECK: movz x6, #:abs_g2:sym // encoding: [0bAAA00110,A,0b110AAAAA,0xd2]
34 movz x8, #:abs_g3:sym
35 // CHECK: movz x8, #:abs_g3:sym // encoding: [0bAAA01000,A,0b111AAAAA,0xd2]
H A Delf-reloc-movw.s4 movz x0, #:abs_g0:some_label
7 movz x3, #:abs_g1:some_label
10 movz x3, #:abs_g2:some_label
13 movz x7, #:abs_g3:some_label
16 movz x13, #:abs_g0_s:some_label
19 movz x19, #:abs_g1_s:some_label
22 movz x19, #:abs_g2_s:some_label
H A Djump-table.s19 movz x0, #1
25 movz x0, #2
28 movz x0, #4
31 movz x0, #8
H A Darm64-tls-relocs.s10 movz x15, #:gottprel_g1:var
11 // CHECK: movz x15, #:gottprel_g1:var // encoding: [0bAAA01111,A,0b101AAAAA,0x92]
43 movz x3, #:tprel_g2:var
45 // CHECK: movz x3, #:tprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92]
54 movz x5, #:tprel_g1:var
56 movz w7, #:tprel_g1:var
57 // CHECK: movz x5, #:tprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92]
61 // CHECK: movz w7, #:tprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12]
80 movz x11, #:tprel_g0:var
82 movz w1
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H A Dtls-relocs.s6 movz x1, #:dtprel_g2:var
8 movz x3, #:dtprel_g2:var
11 // CHECK: movz x1, #:dtprel_g2:var // encoding: [0bAAA00001,A,0b110AAAAA,0x92]
15 // CHECK: movz x3, #:dtprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92]
28 movz x5, #:dtprel_g1:var
30 movz w7, #:dtprel_g1:var
33 // CHECK: movz x5, #:dtprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92]
37 // CHECK: movz w7, #:dtprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12]
60 movz x11, #:dtprel_g0:var
62 movz w1
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H A Darm64-aliases.s151 movz x0, #0
152 movz x0, #0, lsl #16
153 movz x0, #0, lsl #32
154 movz x0, #0, lsl #48
155 movz w0, #0
156 movz w0, #0, lsl #16
158 ; CHECK: movz x0, #0x0, lsl #16
159 ; CHECK: movz x0, #0x0, lsl #32
160 ; CHECK: movz x0, #0x0, lsl #48
162 ; CHECK: movz w
[all...]
/external/capstone/suite/MC/Mips/
H A Dmicromips-movcond-instructions-EB.s.cs2 0x00,0xe6,0x48,0x58 = movz $9, $6, $7
H A Dmicromips-movcond-instructions.s.cs2 0xe6,0x00,0x58,0x48 = movz $9, $6, $7
/external/valgrind/none/tests/mips64/
H A Dchange_fp_mode.stdout.exp38 movz.s $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
39 movz.s $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
40 movz.s $f1, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
41 movz.s $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
42 movz.s $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
43 movz.s $f1, $f2, $0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
44 movz.d $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
45 movz.d $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
46 movz.d $f1, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
47 movz
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/external/llvm/test/MC/Mips/
H A Dmicromips-movcond-instructions.s12 # CHECK-EL: movz $9, $6, $7 # encoding: [0xe6,0x00,0x58,0x48]
19 # CHECK-EB: movz $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x58]
23 movz $9, $6, $7
H A Dmicromips-fpu-instructions.s58 # CHECK-EL: movz.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x20]
59 # CHECK-EL: movz.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x21]
123 # CHECK-EB: movz.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x78]
124 # CHECK-EB: movz.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x78]
184 movz.s $f4, $f6, $7
185 movz.d $f4, $f6, $7
/external/boringssl/src/crypto/fipsmodule/aes/asm/
H A Daes-586.pl257 &movz ($s[2],&HB($s[0]));
262 &movz ($s[1],&HB($v1));
270 &movz ($v0,&HB($v1));
273 &movz ($v0,&HB($v1));
282 &movz ($v1,&HB($v0));
285 &movz ($v1,&HB($v0));
294 &movz ($v0,&HB($v1));
297 &movz ($v0,&HB($v1));
309 &movz ($v0,&LB($s0)); # 3, 2, 1, 0*
312 &movz (
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/external/llvm/test/MC/Mips/mips3/
H A Dinvalid-mips4.s26 movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
27 movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
28 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips5.s27 movz $a1,$s6,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
28 movz.d $f12,$f29,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
29 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips32r6/
H A Dinvalid-mips32.s23 movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
24 movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
25 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/valgrind/none/tests/mips32/
H A DMoveIns.stdout.exp306 movz.s $f0, $f2, $t3 :: fs rt 0x0
307 movz.s $f0, $f2, $t3 :: fs rt 0x0
308 movz.s $f0, $f2, $t3 :: fs rt 0x0
309 movz.s $f0, $f2, $t3 :: fs rt 0x0
310 movz.s $f0, $f2, $t3 :: fs rt 0x0
311 movz.s $f0, $f2, $t3 :: fs rt 0xc0e96d19
312 movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
313 movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
314 movz.s $f0, $f2, $t3 :: fs rt 0x0
315 movz
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/external/llvm/test/MC/Mips/mips2/
H A Dinvalid-mips32.s36 movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
37 movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
38 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips32r2.s45 movz $a1,$s6,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
46 movz.d $f12,$f29,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
47 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips4.s66 movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
67 movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
68 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips5.s64 movz $a1,$s6,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
65 movz.d $f12,$f29,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
66 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips64.s35 movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
36 movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
37 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/boringssl/src/crypto/fipsmodule/sha/asm/
H A Dsha1-armv8.pl81 movz $K,#0xeba1
106 movz $K,#0xc1d6
132 movz $K,#0xbcdc
207 movz $K,#0x7999
/external/llvm/test/ExecutionEngine/RuntimeDyld/AArch64/
H A DMachO_ARM64_relocations.s9 movz w0, #0
/external/vixl/test/
H A Dtest-code-generation-scopes.cc103 __ movz(aarch64::x1, 1);
547 __ movz(aarch64::x1, 1);
577 __ movz(aarch64::x0, 0);
613 __ movz(aarch64::x1, 1);

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