Searched refs:outw (Results 1 - 25 of 43) sorted by relevance

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/external/syslinux/gpxe/src/drivers/net/
H A D3c5x9.c42 outw(RX_DISABLE, nic->ioaddr + EP_COMMAND);
43 outw(RX_DISCARD_TOP_PACK, nic->ioaddr + EP_COMMAND);
46 outw(TX_DISABLE, nic->ioaddr + EP_COMMAND);
47 outw(STOP_TRANSCEIVER, nic->ioaddr + EP_COMMAND);
49 outw(RX_RESET, nic->ioaddr + EP_COMMAND);
50 outw(TX_RESET, nic->ioaddr + EP_COMMAND);
51 outw(C_INTR_LATCH, nic->ioaddr + EP_COMMAND);
52 outw(SET_RD_0_MASK, nic->ioaddr + EP_COMMAND);
53 outw(SET_INTR_MASK, nic->ioaddr + EP_COMMAND);
54 outw(SET_RX_FILTE
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H A D3c595.c77 outw(RX_DISABLE, BASE + VX_COMMAND);
78 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND);
80 outw(TX_DISABLE, BASE + VX_COMMAND);
81 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
83 outw(RX_RESET, BASE + VX_COMMAND);
85 outw(TX_RESET, BASE + VX_COMMAND);
87 outw(C_INTR_LATCH, BASE + VX_COMMAND);
88 outw(SET_RD_0_MASK, BASE + VX_COMMAND);
89 outw(SET_INTR_MASK, BASE + VX_COMMAND);
90 outw(SET_RX_FILTE
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H A D3c515.c100 outw(SelectWindow + (win_num), nic->ioaddr + EL3_CMD)
325 outw(TxReset, nic->ioaddr + EL3_CMD);
330 outw(RxReset, nic->ioaddr + EL3_CMD);
336 outw(SetStatusEnb | 0x00, nic->ioaddr + EL3_CMD);
350 outw(0, nic->ioaddr + i);
354 outw(StartCoax, nic->ioaddr + EL3_CMD);
356 outw((inw(nic->ioaddr + Wn4_Media) & ~(Media_10TP | Media_SQE)) |
360 /* outw(StatsDisable, nic->ioaddr + EL3_CMD);*/
370 outw(0x0040, nic->ioaddr + Wn4_NetDiag);
395 outw(SetRxFilte
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H A Dcs89x0.c112 outw(portno, eth_nic_base + ADD_PORT);
118 outw(portno, eth_nic_base + ADD_PORT);
119 outw(value, eth_nic_base + DATA_PORT);
275 outw(TX_AFTER_ALL, eth_nic_base + TX_CMD_PORT);
276 outw(ETH_ZLEN, eth_nic_base + TX_LEN_PORT);
345 outw(PP_CS8920_ISAINT, eth_nic_base + ADD_PORT);
350 outw(PP_CS8920_ISAMemB, eth_nic_base + ADD_PORT);
381 outw(PP_ChipID, eth_nic_base + ADD_PORT);
407 outw(TX_AFTER_ALL, eth_nic_base + TX_CMD_PORT);
408 outw(s
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H A Ddepca.c472 outw(CSR0, ioaddr + DEPCA_ADDR);\
473 outw(STOP, ioaddr + DEPCA_DATA)
504 outw(CSR1, nic->ioaddr + DEPCA_ADDR); /* initialisation block address LSW */
505 outw((u16) (lp.sh_mem & LA_MASK), nic->ioaddr + DEPCA_DATA);
506 outw(CSR2, nic->ioaddr + DEPCA_ADDR); /* initialisation block address MSW */
507 outw((u16) ((lp.sh_mem & LA_MASK) >> 16), nic->ioaddr + DEPCA_DATA);
508 outw(CSR3, nic->ioaddr + DEPCA_ADDR); /* ALE control */
509 outw(ACON, nic->ioaddr + DEPCA_DATA);
510 outw(CSR0, nic->ioaddr + DEPCA_ADDR); /* Point back to CSR0 */
519 outw(CSR
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H A Dsundance.c299 outw(inw(BASE + MACCtrl0) | EnbFullDuplex,
312 outw(inw(BASE + MACCtrl0) | duplex ? 0x20 : 0,
378 outw(addr16, BASE + StationAddr);
380 outw(addr16, BASE + StationAddr + 2);
382 outw(addr16, BASE + StationAddr + 4);
385 outw(sdc->mtu + 14, BASE + MaxFrameSize);
391 outw(0, BASE + DownCounter);
399 outw(RxEnable | TxEnable, BASE + MACCtrl1);
433 outw(intr_status, nic->ioaddr + IntrEnable);
436 outw(
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H A Deepro.c330 outw(rx_start = (RCV_LOWER_LIMIT << 8), nic->ioaddr + RCV_BAR);
331 outw(((RCV_UPPER_LIMIT << 8) | 0xFE), nic->ioaddr + RCV_STOP);
333 outw((RCV_LOWER_LIMIT << 8), nic->ioaddr + HOST_ADDRESS_REG);
334 outw(0, nic->ioaddr + IO_PORT);
336 outw((XMT_LOWER_LIMIT << 8), nic->ioaddr + xmt_bar);
359 outw(rcv_car, nic->ioaddr + HOST_ADDRESS_REG);
400 outw(rcv_car - 1, nic->ioaddr + RCV_STOP);
431 outw(last, nic->ioaddr + HOST_ADDRESS_REG);
432 outw(XMT_CMD, nic->ioaddr + IO_PORT);
433 outw(
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H A Dtlan.h353 outw(internal_addr, base_addr + TLAN_DIO_ADR);
363 outw(internal_addr, base_addr + TLAN_DIO_ADR);
373 outw(internal_addr, base_addr + TLAN_DIO_ADR);
383 outw(internal_addr, base_addr + TLAN_DIO_ADR);
393 outw(internal_addr, base_addr + TLAN_DIO_ADR);
394 outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
403 outw(internal_addr, base_addr + TLAN_DIO_ADR);
H A D3c90x.c78 outw(val, ioaddr + regCommandIntStatus_w);
160 outw(address, inf_3c90x->IOAddr + regEepromCommand_0_w);
215 outw(0, inf_3c90x->IOAddr + regStationMask_2_3w + 0);
216 outw(0, inf_3c90x->IOAddr + regStationMask_2_3w + 2);
217 outw(0, inf_3c90x->IOAddr + regStationMask_2_3w + 4);
625 outw(cmdRxDisable, inf_3c90x->IOAddr + regCommandIntStatus_w);
626 outw(cmdTxDisable, inf_3c90x->IOAddr + regCommandIntStatus_w);
674 outw(tmp, inf_3c90x->IOAddr + regResetOptions_2_w);
849 outw(cmdRxDisable, inf_3c90x->IOAddr + regCommandIntStatus_w);
850 outw(cmdTxDisabl
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H A Dsmc9000.c49 # define _outw outw
149 outw( mii_reg | bits[i], ioaddr+MII_REG );
154 outw( mii_reg | bits[i] | MII_MCLK, ioaddr+MII_REG );
161 outw( mii_reg, ioaddr+MII_REG );
273 outw( mii_reg | bits[i], ioaddr+MII_REG );
278 outw( mii_reg | bits[i] | MII_MCLK, ioaddr+MII_REG );
285 outw( mii_reg, ioaddr+MII_REG );
405 outw( rpc_cur_mode, ioaddr + RPC_REG );
501 outw( rpc_cur_mode, ioaddr + RPC_REG );
H A Dvia-rhine.c867 outw (ReadMIItmp, wMIIDATA);
953 outw(intr_status, nic->ioaddr + IntrEnable);
956 outw(0x0010, nic->ioaddr + 0x84);
1039 outw(CR_SFRST, byCR0);
1132 outw (CR_FDX, byCR0);
1184 outw(CR_STOP, byCR0);
1274 outw (CR_FDX, byCR0);
1280 outw ((CRbak | CR_STRT | CR_TXON | CR_RXON | CR_DPOLL), byCR0);
1283 outw (0, byIMR0);
1310 outw(intr_statu
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H A Dpcnet32.c268 outw(index, addr + PCNET32_WIO_RAP);
274 outw(index, addr + PCNET32_WIO_RAP);
275 outw(val, addr + PCNET32_WIO_RDP);
280 outw(index, addr + PCNET32_WIO_RAP);
286 outw(index, addr + PCNET32_WIO_RAP);
287 outw(val, addr + PCNET32_WIO_BDP);
297 outw(val, addr + PCNET32_WIO_RAP);
307 outw(88, addr + PCNET32_WIO_RAP);
H A Dpnic.c54 outw ( input_length, pnic->ioaddr + PNIC_REG_LEN );
59 outw ( command, pnic->ioaddr + PNIC_REG_CMD );
H A Dtlan.c340 outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
507 outw(host_int, BASE + TLAN_HOST_INT);
838 outw(data, BASE + TLAN_HOST_CMD);
885 outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
924 outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
981 outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
1107 outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1185 outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
1221 outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
1257 outw(TLAN_NET_SI
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H A D3c509.h75 #define GO_WINDOW(b,x) outw(WINDOW_SELECT|(x), (b)+EP_COMMAND)
H A Ddmfe.c595 outw(addrptr[0], ioaddr);
597 outw(addrptr[1], ioaddr);
599 outw(addrptr[2], ioaddr);
617 outw(hash_table[i], ioaddr);
887 outw(phy_data, ioaddr);
/external/syslinux/com32/include/sys/
H A Dio.h32 static inline void outw(uint16_t v, uint16_t p) function
34 asm volatile ("outw %0,%1"::"a" (v), "Nd"(p));
/external/syslinux/gpxe/src/drivers/bus/
H A Dvirtio-pci.c27 outw(queue_index, ioaddr + VIRTIO_PCI_QUEUE_SEL);
/external/syslinux/gpxe/src/include/gpxe/
H A Dvirtio-pci.h81 outw(queue_index, ioaddr + VIRTIO_PCI_QUEUE_NOTIFY);
88 outw(queue_index, ioaddr + VIRTIO_PCI_QUEUE_SEL);
H A Dio.h337 void outw ( uint16_t data, volatile uint16_t *io_addr );
338 #define outw( data, io_addr ) \ macro
339 IOAPI_WRITE ( outw, uint16_t, data, io_addr, "IO", 4 )
488 #define outw_p( data, io_addr ) OUTX_P ( outw, data, io_addr )
/external/libchrome/base/strings/
H A Dstringprintf_unittest.cc97 std::wstring outw; local
98 SStringPrintf(&outw, L"%ls", srcw);
99 EXPECT_STREQ(srcw, outw.c_str());
/external/syslinux/gpxe/src/arch/i386/core/
H A Dx86_io.c87 PROVIDE_IOAPI_INLINE ( x86, outw );
/external/syslinux/gpxe/src/arch/x86/include/gpxe/
H A Dpcidirect.h120 outw ( value, PCIDIRECT_CONFIG_DATA + ( where & 2 ) );
/external/syslinux/gpxe/src/include/gpxe/efi/
H A Defi_io.h128 IOAPI_INLINE ( efi, outw ) ( uint16_t data, volatile uint16_t *io_addr ) {
/external/syslinux/gpxe/src/interface/efi/
H A Defi_io.c196 PROVIDE_IOAPI_INLINE ( efi, outw );

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