/external/libvpx/libvpx/vpx_dsp/mips/ |
H A D | idct32x32_msa.c | 44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); 50 DOTP_CONST_PAIR(reg1, reg7, cospi_28_64, cospi_4_64, reg1, reg7); 52 BUTTERFLY_4(reg1, reg7, reg3, reg5, vec1, vec3, vec2, vec0); 65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); 66 DOTP_CONST_PAIR(reg0, reg7, cospi_30_64, cospi_2_64, reg0, reg7); 77 reg5 = reg7 + reg3; 78 reg7 128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 354 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 434 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local [all...] |
H A D | idct16x16_msa.c | 16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; local 19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); 23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1, 24 reg2, reg3, reg4, reg5, reg6, reg7); 41 DOTP_CONST_PAIR(reg9, reg7, cospi_14_64, cospi_18_64, loc2, loc3); 45 reg7 = reg15 - loc3; 65 DOTP_CONST_PAIR(reg7, reg9, cospi_24_64, cospi_8_64, reg7, reg9); 73 loc0 = reg7 + reg11; 74 reg11 = reg7 110 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; local [all...] |
/external/libyuv/files/source/ |
H A D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 109 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); 111 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); 131 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); 147 res8 = (v16u8)__msa_ilvr_w((v4i32)reg7, (v4i32)reg3); 148 res9 = (v16u8)__msa_ilvl_w((v4i32)reg7, (v4i32)reg3); 166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 190 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); 192 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); 212 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); [all...] |
H A D | scale_msa.cc | 133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 164 reg7 = (v8u16)__msa_pckod_d((v2i64)reg3, (v2i64)reg1); 166 reg5 += reg7;
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H A D | row_msa.cc | 826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; local 899 reg7 = reg1 * const_0x70; 903 reg7 += const_0x8080; 917 reg7 -= reg9; 921 reg7 = (v8u16)__msa_srai_h((v8i16)reg7, 8); 924 dst0 = (v16u8)__msa_pckev_b((v16i8)reg7, (v16i8)reg6); 1237 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 1267 reg7 = (v4u32)__msa_ilvl_h(zero, (v8i16)vec7); 1275 reg7 * 2666 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; local [all...] |
/external/vixl/src/aarch64/ |
H A D | operands-aarch64.h | 480 const CPURegister& reg7 = NoReg, 494 const CPURegister& reg7 = NoCPUReg,
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H A D | assembler-aarch64.cc | 4754 const CPURegister& reg7, 4762 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; 4793 const CPURegister& reg7, 4802 match &= !reg7.IsValid() || reg7.IsSameSizeAndType(reg1);
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/external/elfutils/tests/ |
H A D | run-addrcfi.sh | 40 integer reg7 (%edi): same_value 87 integer reg7 (%edi): same_value 139 integer reg7 (%rsp): location expression: call_frame_cfa stack_value 205 integer reg7 (%rsp): location expression: call_frame_cfa stack_value 309 integer reg7 (r7): undefined 1331 integer reg7 (r7): undefined 2359 integer reg7 (r7): undefined 3385 integer reg7 (%r7): same_value 3462 integer reg7 (%r7): same_value 3540 integer reg7 (r [all...] |
/external/v8/src/arm64/ |
H A D | assembler-arm64.cc | 230 const CPURegister& reg7, const CPURegister& reg8) { 237 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; 267 const CPURegister& reg7, const CPURegister& reg8) { 275 match &= !reg7.IsValid() || reg7.IsSameSizeAndType(reg1); 227 AreAliased(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) argument 264 AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) argument
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H A D | assembler-arm64.h | 361 const CPURegister& reg7 = NoReg, 374 const CPURegister& reg7 = NoCPUReg,
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/external/elfutils/libdw/ |
H A D | known-dwarf.h | 527 DWARF_ONE_KNOWN_DW_OP (reg7, DW_OP_reg7) \
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/external/v8/src/arm/ |
H A D | macro-assembler-arm.cc | 3741 Register reg7, 3745 reg7.is_valid() + reg8.is_valid(); 3754 if (reg7.is_valid()) regs |= reg7.bit(); 3735 AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6, Register reg7, Register reg8) argument
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H A D | macro-assembler-arm.h | 79 Register reg7 = no_reg,
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/external/v8/src/ia32/ |
H A D | macro-assembler-ia32.cc | 2651 Register reg7, 2655 reg7.is_valid() + reg8.is_valid(); 2664 if (reg7.is_valid()) regs |= reg7.bit(); 2645 AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6, Register reg7, Register reg8) argument
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H A D | macro-assembler-ia32.h | 50 Register reg6 = no_reg, Register reg7 = no_reg,
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/external/v8/src/x87/ |
H A D | macro-assembler-x87.cc | 2497 Register reg7, 2501 reg7.is_valid() + reg8.is_valid(); 2510 if (reg7.is_valid()) regs |= reg7.bit(); 2491 AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6, Register reg7, Register reg8) argument
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H A D | macro-assembler-x87.h | 53 Register reg6 = no_reg, Register reg7 = no_reg,
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/external/v8/src/ppc/ |
H A D | macro-assembler-ppc.cc | 4261 Register reg5, Register reg6, Register reg7, Register reg8, 4265 reg7.is_valid() + reg8.is_valid() + reg9.is_valid() + 4275 if (reg7.is_valid()) regs |= reg7.bit(); 4260 AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6, Register reg7, Register reg8, Register reg9, Register reg10) argument
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H A D | macro-assembler-ppc.h | 69 Register reg6 = no_reg, Register reg7 = no_reg,
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/external/v8/src/x64/ |
H A D | macro-assembler-x64.cc | 5060 Register reg7, 5064 reg7.is_valid() + reg8.is_valid(); 5073 if (reg7.is_valid()) regs |= reg7.bit(); 5054 AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6, Register reg7, Register reg8) argument
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H A D | macro-assembler-x64.h | 74 Register reg7 = no_reg,
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/external/v8/src/mips/ |
H A D | macro-assembler-mips.cc | 6400 Register reg5, Register reg6, Register reg7, Register reg8, 6404 reg7.is_valid() + reg8.is_valid() + reg9.is_valid() + 6414 if (reg7.is_valid()) regs |= reg7.bit(); 6399 AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6, Register reg7, Register reg8, Register reg9, Register reg10) argument
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H A D | macro-assembler-mips.h | 105 Register reg6 = no_reg, Register reg7 = no_reg,
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/external/v8/src/s390/ |
H A D | macro-assembler-s390.cc | 5260 Register reg5, Register reg6, Register reg7, Register reg8, 5264 reg7.is_valid() + reg8.is_valid() + reg9.is_valid() + 5274 if (reg7.is_valid()) regs |= reg7.bit(); 5259 AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6, Register reg7, Register reg8, Register reg9, Register reg10) argument
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/external/v8/src/mips64/ |
H A D | macro-assembler-mips64.cc | 6807 Register reg5, Register reg6, Register reg7, Register reg8, 6811 reg7.is_valid() + reg8.is_valid() + reg9.is_valid() + 6821 if (reg7.is_valid()) regs |= reg7.bit(); 6806 AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6, Register reg7, Register reg8, Register reg9, Register reg10) argument
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